![](/images/new-backgrounds/1206493/20649319x1.webp)
Overview
Figure 1. TMS320C645x DSP Block Diagram
EMIFA
DDR2 memory
controller
PLL2
GPIO
Other peripherals
EDMA
controller
Boot
configuration
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| L1P |
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| cache/SRAM |
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| L2 memory | L1 program memory controller |
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| Advanced | ||||
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| controller | Cache control |
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| event | |||
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| triggering | ||||
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| Bandwidth management |
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| memory | Cache |
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| (AET) | |||||
| control | Memory protection |
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| Bandwidth |
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resource | L2 | management | C64x+ CPU |
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Memory | IDMA |
| Instruction fetch |
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protection |
| SPLOOP buffer |
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central |
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| 16/32−bit instruction dispatch |
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| Instruction decode |
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| Data path A |
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| Data path B |
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Switched |
| External |
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| memory | L1 | S1 | M1 | D1 | D2 | M2 | S2 | L2 | |
| controller | |||||||||
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| Configuration |
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| Register file A |
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| Register file B |
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| registers |
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| Master |
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| DMA | L1 data memory controller |
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| Interrupt | ||||
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| Slave | Cache control |
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| and exception | ||||
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| DMA |
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| controller | ||||
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| Memory protection |
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| Power control | |||||||
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| Bandwidth management |
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PLL2 |
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| L1D |
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| cache/SRAM |
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Some GPIO pins are MUXed with other device pins. Refer to the
10 | SPRU724 |