Toshiba TMP92CM22FG, TLCS-900

TMP92CM22

2007-02-16

92CM22-258

Contents

Main TLCS-900/H1 Series TMP92CM22FG Page TMP92CM22 2007-02-16 92CM22-1 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics RESTRICTIONS ON PRODUCT USE TMP92CM22 2007-02-16 92CM22-2 TMP92CM22 2007-02-16 92CM22-3 Figure 1.1 TMP92CM22 Block Diagram TMP92CM22 2. Pin Assignment and Functions 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CM22FG. Figure 2.1.1 Pin Assignment Diagram (100-Pin QFP) TMP92CM22 QFP100 Top view 2.2 Pin Names and Functions TMP92CM22 2007-02-16 92CM22-6 Table 2.2.2 Pin Names and Functions (2/2) Pin Names Number of Pins I/O Functions 3. Operation 3.1 CPU 3.1.1 Outline TMP92CM22 2007-02-16 92CM22-8 3.1.2 Reset Operation TMP92CM22 2007-02-16 92CM22-9 3.1.3 Outline of Operation Mode TMP92CM22 2007-02-16 92CM22-10 3.2 Memory Map 3.3 Clock Function and Standby Function TMP92CM22 2007-02-16 92CM22-12 TMP92CM22 2007-02-16 92CM22-13 3.3.1 Block Diagram of System Clock TMP92CM22 2007-02-16 92CM22-14 3.3.2 SFRs TMP92CM22 2007-02-16 92CM22-15 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-16 3.3.3 System Clock Controller TMP92CM22 2007-02-16 92CM22-17 3.3.4 Clock Doubler (PLL) TMP92CM22 2007-02-16 92CM22-18 TMP92CM22 2007-02-16 92CM22-19 3.3.5 Noise Reduction Circuits TMP92CM22 2007-02-16 92CM22-20 TMP92CM22 2007-02-16 92CM22-21 TMP92CM22 2007-02-16 92CM22-22 3.3.6 Standby Controller TMP92CM22 2007-02-16 92CM22-23 TMP92CM22 2007-02-16 92CM22-24 TMP92CM22 2007-02-16 92CM22-25 TMP92CM22 2007-02-16 92CM22-26 TMP92CM22 2007-02-16 92CM22-27 Table 3.3.5 Input Buffer State Table TMP92CM22 2007-02-16 92CM22-28 Table 3.3.6 Output Buffer State Table TMP92CM22 3.4 Interrupt TMP92CM22 2007-02-16 92CM22-30 TMP92CM22 2007-02-16 92CM22-31 3.4.1 General-purpose Interrupt Processing TMP92CM22 2007-02-16 92CM22-32 Table 3.4.1 TMP92CM22 Interrupt Vectors and Micro DMA Start Vectors Default Priority Value Address Refer to Vector Micro DMA Start Vec tor TMP92CM22 2007-02-16 92CM22-33 TMP92CM22 2007-02-16 92CM22-34 3.4.2 Micro DMA TMP92CM22 2007-02-16 92CM22-35 TMP92CM22 2007-02-16 92CM22-36 TMP92CM22 2007-02-16 92CM22-37 TMP92CM22 2007-02-16 92CM22-38 3.4.3 Interrupt Controller Operation TMP92CM22 2007-02-16 92CM22-39 TMP92CM22 2007-02-16 92CM22-40 (1) Interrupt priority setting registers TMP92CM22 2007-02-16 92CM22-41 IxxM2 IxxM1 IxxM0 Function (Write) TMP92CM22 2007-02-16 92CM22-42 TMP92CM22 2007-02-16 92CM22-43 TMP92CM22 2007-02-16 92CM22-44 TMP92CM22 2007-02-16 92CM22-45 TMP92CM22 2007-02-16 92CM22-46 Page TMP92CM22 2007-02-16 92CM22-48 TMP92CM22 2007-02-16 92CM22-49 3.5 Port Function TMP92CM22 2007-02-16 92CM22-50 TMP92CM22 2007-02-16 92CM22-51 TMP92CM22 2007-02-16 92CM22-52 3.5.1 Port 1 (P10 to P17) TMP92CM22 2007-02-16 92CM22-53 TMP92CM22 2007-02-16 92CM22-54 3.5.2 Port 4 (P40 to P47) TMP92CM22 2007-02-16 92CM22-55 TMP92CM22 2007-02-16 92CM22-56 3.5.3 Port 5 (P50 to P57) TMP92CM22 2007-02-16 92CM22-57 TMP92CM22 2007-02-16 92CM22-58 3.5.4 Port 6 (P60 to P67) TMP92CM22 2007-02-16 92CM22-59 TMP92CM22 2007-02-16 92CM22-60 3.5.5 Port 7 (P70 to P76) TMP92CM22 2007-02-16 92CM22-61 TMP92CM22 2007-02-16 92CM22-62 3.5.6 Port 8 (P80 to P83) TMP92CM22 2007-02-16 92CM22-63 3.5.7 Port 9 (P90 to P92) TMP92CM22 2007-02-16 92CM22-64 TMP92CM22 2007-02-16 92CM22-65 3.5.8 Port A (PA0 to PA2, PA7) TMP92CM22 2007-02-16 92CM22-66 3.5.9 Port C (PC0, PC1, PC3, PC5, and PC6) TMP92CM22 2007-02-16 92CM22-67 TMP92CM22 2007-02-16 92CM22-68 TMP92CM22 2007-02-16 92CM22-69 Port C Register 7 6 5 4 3 2 1 0 Port C Control Register 7 6 5 4 3 2 1 0 Port C Function Register 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-70 3.5.10 Port D (PD0 to PD3) TMP92CM22 2007-02-16 92CM22-71 TMP92CM22 2007-02-16 92CM22-72 TMP92CM22 2007-02-16 92CM22-73 3.5.11 Port F (PF0 to PF7) TMP92CM22 2007-02-16 92CM22-74 TMP92CM22 2007-02-16 92CM22-75 TMP92CM22 2007-02-16 92CM22-76 TMP92CM22 2007-02-16 92CM22-77 3.5.12 Port G (PG0 to PG7) TMP92CM22 92CM22-78 3.6 Memory Controller 3.6.1 Function TMP92CM22 92CM22-79 2007-02-16 3.6.2 Control Register and Operation after Reset Release TMP92CM22 92CM22-80 2007-02-16 3.6.3 Basic Functions and Register Setting TMP92CM22 92CM22-81 2007-02-16 TMP92CM22 92CM22-82 2007-02-16 TMP92CM22 92CM22-83 2007-02-16 CPU Data Data Size (Bit) Start Memory Side (Bit) CPU TMP92CM22 92CM22-84 2007-02-16 TMP92CM22 92CM22-85 2007-02-16 TMP92CM22 92CM22-86 2007-02-16 TMP92CM22 92CM22-87 2007-02-16 TMP92CM22 92CM22-88 2007-02-16 TMP92CM22 92CM22-89 2007-02-16 TMP92CM22 92CM22-90 2007-02-16 3.6.4 ROM Control (Page mode) TMP92CM22 92CM22-91 2007-02-16 3.6.5 List of Registers TMP92CM22 92CM22-92 2007-02-16 BnCSH (n = 0, 1, 3) TMP92CM22 92CM22-93 2007-02-16 BEXCSL BEXCSH 7 6 5 4 3 2 1 0 TMP92CM22 92CM22-94 2007-02-16 TMP92CM22 92CM22-95 2007-02-16 TMP92CM22 92CM22-96 2007-02-16 Table 3.6.1 Control Register TMP92CM22 92CM22-97 2007-02-16 3.6.6 Caution TMP92CM22 92CM22-98 2007-02-16 TMP92CM22 2007-02-16 92CM22-99 3.7 8-Bit Timers (TMRA) TMP92CM22 2007-02-16 92CM22-100 3.7.1 Block Diagrams TMP92CM22 2007-02-16 92CM22-101 TMP92CM22 2007-02-16 92CM22-102 3.7.2 Operation of Each Circuit TMP92CM22 2007-02-16 92CM22-103 TMP92CM22 2007-02-16 92CM22-104 TMP92CM22 2007-02-16 92CM22-105 3.7.3 SFRs TMP92CM22 2007-02-16 92CM22-106 TMP92CM22 2007-02-16 92CM22-107 TMP92CM22 2007-02-16 92CM22-108 TMP92CM22 2007-02-16 92CM22-109 TMP92CM22 2007-02-16 92CM22-110 TMP92CM22 2007-02-16 92CM22-111 3.7.4 Operation in Each Mode TMP92CM22 2007-02-16 92CM22-112 TMP92CM22 2007-02-16 92CM22-113 TMP92CM22 2007-02-16 92CM22-114 TMP92CM22 2007-02-16 92CM22-115 TMP92CM22 2007-02-16 92CM22-116 TMP92CM22 2007-02-16 92CM22-117 TMP92CM22 2007-02-16 92CM22-118 TMP92CM22 2007-02-16 92CM22-119 Table 3.7.4 Relationship of PWM Cycle and 2n Counter : Dont care TMP92CM22 3.8 16-Bit Timer/Event Counters (TMRB) TMP92CM22 2007-02-16 92CM22-121 3.8.1 Block Diagram TMP92CM22 2007-02-16 92CM22-122 TMP92CM22 2007-02-16 92CM22-123 3.8.2 Operation TMP92CM22 2007-02-16 92CM22-124 TMP92CM22 2007-02-16 92CM22-125 TMP92CM22 2007-02-16 92CM22-126 TMP92CM22 2007-02-16 92CM22-127 3.8.3 SFRs TMP92CM22 2007-02-16 92CM22-128 TMP92CM22 2007-02-16 92CM22-129 TMRB1 Mode Register 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-130 TMP92CM22 2007-02-16 92CM22-131 TMP92CM22 2007-02-16 92CM22-132 TMRB0 register 7 6 5 4 3 2 1 0 Figure 3.8.8 Register for TMRB TMRB1 register 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-133 3.8.4 Operation in Each Mode TMP92CM22 2007-02-16 92CM22-134 TMP92CM22 2007-02-16 92CM22-135 TMP92CM22 2007-02-16 92CM22-136 TMP92CM22 2007-02-16 92CM22-137 TMP92CM22 2007-02-16 92CM22-138 TMP92CM22 2007-02-16 92CM22-139 TMP92CM22 2007-02-16 92CM22-140 2007-02-16 92CM22-141 3.9 Serial Channels (SIO) 2007-02-16 92CM22-142 2007-02-16 92CM22-143 3.9.1 Block Diagram 2007-02-16 92CM22-144 2007-02-16 92CM22-145 3.9.2 Operation of Each Circuit 2007-02-16 92CM22-146 2007-02-16 92CM22-147 2007-02-16 92CM22-148 2007-02-16 92CM22-149 2007-02-16 92CM22-150 2007-02-16 92CM22-151 2007-02-16 92CM22-152 2007-02-16 92CM22-153 2007-02-16 92CM22-154 3.9.3 SFRs 2007-02-16 92CM22-155 2007-02-16 92CM22-156 2007-02-16 92CM22-157 2007-02-16 92CM22-158 2007-02-16 92CM22-159 2007-02-16 92CM22-160 2007-02-16 92CM22-161 3.9.4 Operation in Each Mode 2007-02-16 92CM22-162 2007-02-16 92CM22-163 2007-02-16 92CM22-164 2007-02-16 92CM22-165 2007-02-16 92CM22-166 2007-02-16 92CM22-167 2007-02-16 92CM22-168 2007-02-16 92CM22-169 3.9.5 Support for IrDA Mode 2007-02-16 92CM22-170 2007-02-16 92CM22-171 TMP92CM22 2007-02-16 92CM22-172 3.10 Serial Bus Interface (SBI) 3.10.1 Configuration TMP92CM22 2007-02-16 92CM22-173 3.10.2 Control 3.10.3 Data Format in I2C Bus Mode TMP92CM22 2007-02-16 92CM22-174 3.10.4 I2C Bus Mode Control Register TMP92CM22 2007-02-16 92CM22-175 TMP92CM22 2007-02-16 92CM22-176 TMP92CM22 2007-02-16 92CM22-177 TMP92CM22 2007-02-16 92CM22-178 3.10.5 Control in I2C Bus Mode TMP92CM22 2007-02-16 92CM22-179 TMP92CM22 2007-02-16 92CM22-180 TMP92CM22 2007-02-16 92CM22-181 TMP92CM22 2007-02-16 92CM22-182 TMP92CM22 2007-02-16 92CM22-183 TMP92CM22 2007-02-16 92CM22-184 3.10.6 Data Transfer in I2C Bus Mode TMP92CM22 2007-02-16 92CM22-185 TMP92CM22 2007-02-16 92CM22-186 TMP92CM22 2007-02-16 92CM22-187 TMP92CM22 2007-02-16 92CM22-188 TMP92CM22 2007-02-16 92CM22-189 TMP92CM22 2007-02-16 92CM22-190 3.10.7 Clocked-synchronous 8-bit SIO Mode Control TMP92CM22 2007-02-16 92CM22-191 Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Serial Bus Interface 0 Status Register 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-192 TMP92CM22 2007-02-16 92CM22-193 TMP92CM22 2007-02-16 92CM22-194 TMP92CM22 2007-02-16 92CM22-195 TMP92CM22 2007-02-16 92CM22-196 TMP92CM22 2007-02-16 92CM22-197 TMP92CM22 2007-02-16 92CM22-198 TMP92CM22 2007-02-16 92CM22-199 3.11 Analog/Digital Converter TMP92CM22 2007-02-16 92CM22-200 3.11.1 Analog/Digital Converter Registers TMP92CM22 2007-02-16 92CM22-201 TMP92CM22 2007-02-16 92CM22-202 TMP92CM22 2007-02-16 92CM22-203 TMP92CM22 2007-02-16 92CM22-204 TMP92CM22 2007-02-16 92CM22-205 TMP92CM22 2007-02-16 92CM22-206 3.11.2 Description of Operation TMP92CM22 2007-02-16 92CM22-207 TMP92CM22 2007-02-16 92CM22-208 TMP92CM22 2007-02-16 92CM22-209 TMP92CM22 2007-02-16 92CM22-210 TMP92CM22 2007-02-16 92CM22-211 3.12 Watchdog Timer (Runaway detection timer) 3.12.1 Configuration TMP92CM22 2007-02-16 92CM22-212 3.12.2 Operation TMP92CM22 2007-02-16 92CM22-213 3.12.3 Control Registers TMP92CM22 2007-02-16 92CM22-214 TMP92CM22 2007-02-16 92CM22-215 4. Electrical Characteristics 4.1 Absolute Maximum Ratings TMP92CM22 2007-02-16 92CM22-216 DC Characteristics (1/2) Parameter Symbol Condition Min Typ. Max Unit Power supply voltage TMP92CM22 2007-02-16 92CM22-217 DC Characteristics (2/2) Parameter Symbol Condition Min Typ. Max Unit 4.2 AC Characteristics 4.2.1 Basis Bus Cycle Read cycle fSYS = 20 MHz (fc = 40 MHz) fSYS = 125 kHz (fc = 4 MHz) Unit TMP92CM22 2007-02-16 92CM22-219 TMP92CM22 2007-02-16 92CM22-220 TMP92CM22 2007-02-16 92CM22-221 TMP92CM22 2007-02-16 92CM22-222 4.2.2 Page ROM Read Cycle TMP92CM22 2007-02-16 92CM22-223 4.3 AD Conversion Characteristics 4.4 Event Counter (TA0IN, TB1IN0, and TB1IN1) TMP92CM22 2007-02-16 92CM22-224 4.5 Serial Channel Timing (I/O interface mode) TMP92CM22 2007-02-16 92CM22-225 4.6 Interrupt, Capture TMP92CM22 2007-02-16 92CM22-226 4.7 Recommended Oscillation Circuit TMP92CM22 2007-02-16 92CM22-227 TMP92CM22 2007-02-16 92CM22-228 5. Table of Special Function Registers (SFRs) TMP92CM22 2007-02-16 92CM22-229 Address Name Note: Do not access un-named addresses. TMP92CM22 2007-02-16 92CM22-230 TMP92CM22 2007-02-16 92CM22-231 TMP92CM22 2007-02-16 92CM22-232 (1) I/O port (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-233 I/O port (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-234 I/O port (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-235 (2) Interrupt control (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-236 Interrupt control (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-237 (3) DMA controller Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-238 (4) Memory controller (1/2) Symbol Name TMP92CM22 2007-02-16 92CM22-239 Memory controller (2/2) Symbol Name TMP92CM22 2007-02-16 92CM22-240 (5) Clock gear Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-241 (6) 8-bit timer Symbol Name TMP92CM22 2007-02-16 92CM22-242 (7) 16-bit timer (1/2) Symbol Name TMP92CM22 2007-02-16 92CM22-243 16-bit timer (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 2007-02-16 92CM22-244 (8) UART/Serial channel (1/2) Symbol Name TMP92CM22 2007-02-16 92CM22-245 UART/Serial channel (2/2) Symbol Name TMP92CM22 2007-02-16 92CM22-246 (9) I2C bus/Serial channel (1/2) Symbol Name TMP92CM22 2007-02-16 92CM22-247 I2C bus/Serial channel (2/2) Symbol Name TMP92CM22 2007-02-16 92CM22-248 (10) AD converter (1/2) Symbol Name TMP92CM22 2007-02-16 92CM22-249 AD converter (2/2) Symbol Name TMP92CM22 2007-02-16 92CM22-250 (11) Watchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 TMP92CM22 6. Port Section Equivalent Circuit Diagram TMP92CM22 2007-02-16 92CM22-252 TMP92CM22 2007-02-16 92CM22-253 TMP92CM22 2007-02-16 92CM22-254 TMP92CM22 2007-02-16 92CM22-255 7. Points to Note and Restrictions TMP92CM22 2007-02-16 92CM22-256 8. Package Dimensions