TMP92CM22 2007-02-16 92CM22-86
(5) Bus access timing
• External read/write bus cycle (0 waits)
• External read/write bus cycle (1 wait)
CS
WR
RD
Address
in
p
ut
output
Read
Write
CLKOUT
(20 MHz)
D7 to D0
D7 to D0
T1 T2
CS
WR
RD
Address
Output
CLKOUT
(20 MHz)
D7 to D0
D7 to D0
T1 TW
In
p
ut
Read
Write
T2