TMP92CM22 2007-02-16 92CM22-219
(1) Read cycle (0 waits, fc = fOSCH, fFPH = fc/1)
Note: The phase relation between X1 input signal and the other signals is unsettled.
The timing chart above is an example.
CLKOUT
tCL
tTK
tAD
tH
A
WAIT
A
0 to A23
X1
tOSC
CSx
tCYC tCH
tKT
tAR tRK
tHR
tRR
D0 to D31 Data input
RD
tRD
R/W