TMP92CM22 2007-02-16 92CM22-174

3.10.4 I2C Bus Mode Control Register

The following registers are used to control and monitor the operation status when using

the serial bus interface (SBI) in the I2C bus mode.

Serial Bus Interface Control Register 1

7 6 5 4 3 2 1 0

Bit symbol BC2 BC1 BC0 ACK SCK2 SCK1
SCK0/
SWRMON
SBI0CR1
(1240H)
Read/Write W R/W W R/W
After reset 0 0 0 0 0 0 0/1 (Note 3)
Read-
modify-write
instruction is
prohibited.
Function Select number of transferred bits
(Note 1)
Acknowledge
mode
specification
0: Not
generate
1: Generate
Internal serial clock selection and
software reset monitor
(Note 2)

000 n = 5 − kHz (Note4)
001 n = 6 − kHz (Note4)
010 n = 7 − kHz (Note4) System clock: fSYS
011 n = 8 75.8 kHz
100 n = 9 38.5 kHz
101 n = 10 19.4 kHz
110 n = 11 9.73 kHz
fSYS = 20 MHz (output to
SCL pin)
Frequency = [Hz]
111 (Reserved) (Reserved)

0 During software reset
1 Initial data

0 Not generate clock pulse for acknowledge signal
1 Generate clock for acknowledge signal

<ACK> = 0 <ACK> = 1
<BC2:0> Number of
clock
pulses
Data length Number of
clock
pulses
Data length
000 8 8 9 8
001 1 1 2 1
010 2 2 3 2
011 3 3 4 3
100 4 4 5 4
101 5 5 6 5
110 6 6 7 6
111 7 7 8 7
Note 1: Set the <BC2:0> to “000” before switching to a clocked-synchronous 8-bit SIO mode.
Note 2: For the frequency of the SCL line clock, see section 3.10.5 (3) “Serial clock”.
Note 3: Initial data of SCK0 is “0”, SWRMON is “1”.
Note 4: This I2C bus circuit does not support Fast mode, it supports standard mode only. Although the I2C bus circuit
itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C specification is not
guaranteed in that case.

Figure 3.10.3 Register for I2C Bus Mode

Internal serial clock selection <SCK2:0> at write
Software reset state monitor <SWRMON> at read
Acknowledge mode selection
Select number of bits transferred
fSYS
2n + 8