TMP92CM22 2007-02-16 92CM22-220
(2) Write cycle (0 waits, fc = fOSCH, fFPH = fc/1)
Note: The phase relation between X1 input signal and the other signals is unsettled.
The timing chart above is an example.
X1
CLKOUT
A
0 to A23
D0 to D31
WAIT
RD
Data output
tOSC
tCL t
CH
tCYC
tTK tKT
tAW
t
WK
t
WA
t
WW
tDW
t
WD
tRDO
CSx
WRxx
R/W