TMP92CM22

2007-02-16

92CM22-225

4.6 Interrupt, Capture
Note: Symbol “X” in the following table means the period of clock “fSYS”, it’s same period of the system
clock “fSYS” for CPU core. The period of fSYS depends on the clock gear setting or changing
high-speed oscillator/low-speed oscillator and so on.
(1) NMI and INT0 to INT3 interrupts
Varia ble fSYS =
20 MHz
(fc = 40 MHz)
fSYS =
125 kHz
(fc = 4 MHz)
Parameter Symbol
Min Max Min Max Min Max
Unit
INT0 to INT3 low width TINTAL 4X + 40 240 32040
INT0 to INT3 high width TINTAH 4X + 40 240 32040 ns
(2) INT4 to INT5 interrupts
tINTBL
(INT4 to INT5 Low Level Pulse Width)
tINTBH
(INT4 to INT5 High Level Pulse Width)
Varia ble fSYS = 20 MHz
(fc = 40 MHz) Var iabl e fSYS = 20 MHz
(fc = 40 MHz)
Min Min Min Min
Unit
8X + 100 500 8X + 100 500 ns
Valid
3
2
SCLK
Output mode/
in
p
ut risin
g
mode
0 1 2
SCLK
(Input falling mode)
Output data
TXD
Input data
RXD
tSC
Y
tOSS tOHS
tSRD tRDS tHSR
Valid Valid Valid
3 1 0