TMP92CM22 2007-02-16 92CM22-122
Figure 3.8.2 Block Diagram of TMRB1
Timer
flip-flop
control
Match detection
Match
detection
32 16 8 4 2
φT1 φT4 φT16
Run/
clear
φT1
φT4
φT16
TB1MOD<TB1CLK1:0>
Prescaler
clock: φT0
External
interrupt
input INT4
INT5
Selecto
r
Register buffer 12
TB1RUN<TB1RUN>
TB1MOD<TB1CLE>
TB0FF0
Internal data bus
TB1RUN
<TB1RDE>
TB1RUN
<TB1PRUN>
Intenal data bus
TB1MOD
<TB1CPM1:0>
Register 1
INTTB01
TB0FF1
TB1OUT0
TB1OUT1
16-bit timer register
TB1REG0H/L
16-bit comparator
(CP12)
16-bit timer register
TB1RG1H/L
16-bit comparator (CP13)
TB1MOD
<TB1CP0I>
Internal data bus Internal data bus
Register 0
INTTB00
Timer flip-flop
output
Time
r
flip-flop
Overflow
interrupt
INTTBOF0
Capture register 0
TB1CP0H/L Caputure register 1
TB1CP1H/L
TA1OUT
TB1IN0
TB1IN1
(from TMRA23)
16-bit up counter
(UC1)
Count
clock
Interrupt output
Capture,
external interrupt
control