Block Diagram
VT1433B User's Guide
Module Description
LBUS/FIFO
(optional)
Local bus
SRAM 512 kB
DRAM 32 MB
Input 1
Input 2
(optional)
Bus connector
96002
micro-
processor
DMA/
memory
control
Abus | Bbus |
VXI bus
SRAM 512 kB
Hardware
registers
VXI
interface
PLL
clock/ trigger
Tachometer
(optional)
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or... | Source | ||
| (optional) | ||
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Figure 5-1: VT1433B block diagram
For block diagrams of the Arbitrary Source and the Tachometer, see the chapters on the Arbitrary Source option and the Tachometer option.