VT1433B User's Guide
Using the VT1433B
Upon entering the ARM state the VT1433B starts saving new data in its FIFO. It remains in the ARM state until the Sync/Trigger line goes high. If the VT1433B is programmed with a
Upon entering the TRIGGER state the VT1433B continues to collect data into the FIFO, discarding any data prior to the
Upon entering the MEASURE state the VT1433B continues to collect data. The VT1433B also presents the first data from the FIFO to the selected output port, making it available to the controller to read. The VT1433B holds the Sync/Trigger line low as long as it is actively collecting data. In overlap block mode the VT1433B stops taking data as soon as a block of data has been collected, including any programmed pre- or
The measurement initialization and loop may be interrupted at any time with a call to hpe1432_resetMeasure, which puts the module in the TESTED state.
Register-based VXI Devices
The VT1433B is a
Users do not need to access the registers in order to use the VT1433B. The VT1433B’s functions can be more easily accessed using the VT1433B Host Interface Library software. However, if more information about the registers are provided in Appendix A: Register Definitions for reference.