VT1433B User's Guide
Register Definitions
IRQ Status Register: This
Bit | |||
Contents | Status | Logical | |
Address | |||
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Status: Each of these bits indicates the status of a cause of interrupt. A one (1) in a bit position indicates that the corresponding source is actively requesting and interrupt.
Logical Address: This is the device’s current logical address.
IRQ Reset Register: This register is used to resent the interrupt function. It has the following format:
Bit | |||
Contents | Reset | Unused | |
Bits | |||
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Reset Bits: Writing a one (1) to any of these bits will clear the corresponding bit in the IRQ status register. This will not disable subsequent interrupt generation. Clearing all of the IRQ status bits will cause the
Ram
Send Data Register: Reading this register gets the next available word from the measurement data FIFO. The measurement data FIFO is a
Receive Data Register: Writing to this register puts a word into the source data FIFO. The source data FIFO is a
Count Register: The Count register contains an unsigned
Query Response/Command Register: This register is used to send commands to and receive responses from the device. It is implemented as a