Xilinx XAPP721 manual Per Bit Deskew Data Capture Technique

R

Read Datapath

Table 3 shows the read timing analysis at 333 MHz required to determine the delay required on DQ bits for centering DQS in the data valid window.

Table 3: Read Timing Analysis at 333 MHz

Parameter	Value (ps)	Meaning
TCLOCK	3000	Clock period.
TPHASE	1500	Clock phase for DDR data.
TSAMP_BUFIO	350	Sample Window from Virtex-4 data sheet for
		a -12 device. It includes setup and hold for
		an IOB FF, clock jitter, and 150 ps of tap
		uncertainty.
TBUFIO_DCD	100	BUFIO clock resource duty-cycle distortion.
TDQSQ + TQHS	580	Worst case memory uncertainties that
		include VT variations and skew between
		DQS and its associated DQs. Because the
		design includes per bit deskew, realistically
		only a percentage of this number should be
		considered.
TMEM_DCD	150	Duty-cycle distortion.
Tap Uncertainty	0	Tap uncertainty with 75 ps resolution. A
		window detection error of 75 ps can be on
		both ends of the window. This is already
		included in TSAMP_BUFIO.
Total Uncertainties	1180
Window	320	Worst-case window.

Notes:

1.TSAMP_BUFIO is the sampling error over VT for a DDR input register in the IOB when using the BUFIO clocking resource and the IDELAY.

2.All the parameters listed above are uncertainties to be considered when using the per bit calibration technique.

3.Parameters like BUFIO skew, package_skew, pcb_layout_skew, and part of TDQSQ, and TQHS are calibrated out with the per bit calibration technique. Inter-symbol interference and crosstalk, contributors to dynamic skew, are not considered in this analysis.

Per Bit Deskew Data Capture Technique

To ensure reliable data capture in the OCLK and CLKDIV domains in the ISERDES, a training sequence is required after memory initialization. The controller issues a WRITE command to write a known data pattern to a specified memory location. The controller then issues back-to-back read commands to read back the written data from this specified location. The DQ bit 0 ISERDES outputs Q1, Q2, Q3, and Q4 are then compared with the known data pattern. If they do not match, DQ and DQS are delayed by one tap, and the comparison is performed again. The tap increments continue until there is a match. If there is no match even at tap 64, then DQ and DQS are both reset to tap 0. DQS tap is set to one, and both DQS and DQ are delayed in unit tap increments and the comparison is performed after each tap increment until a match is found. With the first detected match, the DQS window count is incremented to 1. DQS continues to be delayed in unit tap increments until a mismatch is detected. The DQS window count is also incremented along with the tap increments to record the width of the data valid window in the FPGA clock domain. DQS is then decremented by half the window count to center DQS edges in the center of the data valid window. With the position of DQS fixed, each DQ bit is then centered with respect to DQS. The dp_dly_slct_done signal is asserted when the centering of all DQ bits associated with its DQS is completed.

62 Memory Interfaces Solution Guide March 2006