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Summary This application note describes a data capture technique for a high-performance DDR2
SDRAMinterface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output
Serializer/Deserializer (OSERDES) features available in every Virtex™-4I/O. This technique
can be used formemor y interfaces with frequencies of 267MHz (533 Mb/s) and above.
Introduction A DDR2 SDRAM interface is source-synchronous where the read data and read strobe are
transmitted edge-aligned. Tocapture this transmitted data using Virtex-4 FPGAs, either the
strobe or the data can be delayed. In this design, the readdata is captured in the delayed
strobe domain and recaptured in the FPGA clock domain in the ISERDES. The received serial,
double data rate (DDR) read data is converted to 4-bit parallel single data rate (SDR) data at
half the frequency of the interface using the ISERDES. Thedifferential strobe is placed on a
clock-capable IO pair in order to access the BUFIOclock resource. The BUFIO clocking
resource routes the delayed read DQS to its associated data ISERDES clock inputs. The write
data and strobe transmitted bythe FPGA use the OSERDES. The OSERDES converts 4-bit
parallel data at half the frequency of the interface to DDR dataat the interface frequency. The
controller, datapath, user interface, andall other FPGA slice logic are clocked at half the
frequency of the interface, resulting in improved design margin at frequencies of 267MHz and
above.

Clocking

Scheme

The clocking scheme for this design includes one digital clock manager (DCM) and two phase-
matched clock dividers (PMCDs) asshown in Figure 1. The controller is clocked at half the
frequency of the interface using CLKdiv_0. Therefore, the address, bank address, and
command signals (RAS_L, CAS_L, and WE_L) are asserted for two clock cycles (knownas
"2T"timing), of the fast memory interface clock. The control signals (CS_L, CKE, and ODT) are
twice the rate (DDR) of the half frequency clock CLKdiv_0, ensuring that the control signalsare
asserted for just one clock cycle of the fast memory interface clock. The clock is forwarded to
the external memory device using the Output Dual Data Rate (ODDR) flip-flops in the Virtex-4
I/O. This forwarded clock is 180degrees out of phase with CLKfast_0. Figure 2 shows the
command and control timing diagram.
Application Note: Virtex-4 Series
XAPP721 (v1.3) February 2, 2006
High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES
Author: Maria George
R
March 2006 Memory Interfaces Solution Guide 55