THE INSTRUCTION SET

PCHL

(Jump Hand l indirect -

 

move Hand l to PC)

(PCH) -

(H)

(PCl) -

(l)

The content of register H is moved to the high-order eight bits of register PC. The content of register l is moved to the low- order eight bits of register PC.

1

o

1

o

o

 

 

 

 

 

 

Cycles:

1

 

 

 

States:

6 (8085), 5 (8080)

 

Addressing:

register

 

 

 

Flags:

none

 

 

5.6.5Stack, 1/0, and Machine Control Group

This group of instructions performs 110, manipu- lates the Stack, and alters internal control flags.

Unless otherwise specified, condition flags are not affected by any Instructions in this group.

PUSH rp (Push)

«SP) - 1) - (rh) «SP) - 2) - (rl) «SP) - (SP) - 2

The content of the high-order register of register pair rp is moved to the memory location whose address is one less than the content of register SP. The content of the low-order register of register pair rp is moved to the memory location whose ad- dress is two less than the content of register SP. The content of register SP is decremented by 2. Note: Register pair rp = SP may not be specified.

1I R I P I 0 I 1 I 0 I Cycles: 3

States: 12 (8085), 11 (8080)

Addressing: reg. indirect

Flags: none

PUSH PSW (Push processor status word)

«SP) - 1) - (A)

 

 

 

«SP)

-

2)0

-

(CY) ,«SP)

-

2)1 -

X

«SP)

-

2)2

-

(P) , «SP) - 2)a - X

«SP)

-

2)4 -

(AC) ,«SP)

-

2)5 -

X

«SP)

-

2)6 ....

(Z) , «SP) -

 

2h -

(S)

(SP) -

(SP) -

2

 

X: Undefined.

The content of register A is moved to the memory location whose address is one less than register SP. The contents of the condition flags are assembled into a pro- cessor status word and the word is moved to the memory location whose address is two less than the content of register SP. The content of register SP is decremented by two.

1 o 1 o 1

Cycles: 3

States: 12 (8085), 11 (8080)

Addressing: reg. indirect

Flags: none

FLAG WORD

0 7 0 6 05 0 4 03 02 01 Do

SZ X IAC I X P X ICy I

X:undefined

POP rp

(Pop)

(rl) - «SP»

(rh) - «SP) + 1) (SP) - (SP) + 2

The content of the memory location, whose address is specified by the content of register SP, is moved to the low-order register of register pair rp. The content of the memory location, whose address is one more than the content of register SP, is moved to the high-order register of register rp. The content of register SP is in- cremented by 2. Note: Register pair rp = SP may not be specified.

1 1 R P 0 0 0 1

Cycles: 3

States: 10

Addressing: reg.indirect

Flags: none

*All mnemonics copyrighted © Intel Corporation 1976.

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Intel MCS-80/85 manual Pchl, Flag Word, Pop

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.