J li\ Lr V V- U V u u u U, ~--r | Intel MCS-80/85 guide

FUNCTIONAL DESCRIPTION

Figure 2-20 illustrates the 81 cycle generated in response to RST 7.5 when a HALT instruction has just been executed and the CPU is in the THALT state, with its various signals floating. There are only two ways the processor can com- pletely exit the THALT state, as shown in Figure 2-11. The first way is for RESET to occur, which always forces the 8085A to TRESET. The second way to exit THALT permanently is for a valid in- terrupt to occur, which will cause the CPU to disable further interrupts by resetting INTE FF, and to then proceed-to M1 • T1 of -the next in- struction. When the HOLD input is activated, the CPU will exit THALT for the duration of THOLD and then return to THALT.

In Figure 2-20 the RST 7.5 line is pulsed during THALT. Since RST 7.5 is a rising-edge-triggered interrupt, it will set an internal latch which is sampled during CLK = "1" of every THALT state (as well as during CLK = "1" two T states before any M1 • T1')The fact that the latched in- terrupt was high (assuming that INTE FF = 1 and the RST 7.5 mask = 0) will force the CPU to exit the THALT state at the end of the next CLK period, and to enter M1 • T1.

This completes our analysis of the timing of each of the seven types of machine cycles.

M1 (OF)

M2 (HALT)

M1 (81)

M2(MW)

SIGNALS

T3

T4

T1

THAlT

THAlT

T1

T2

T3

T4

T5

T6

T1

T2

ClK

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RST 7.5

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~

101M

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AS·A15

(PC·1)H

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PCH

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IN

OUT

OUT

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FIGURE 2·20HALT STATE AND BUS IDLE MACHINE CYCLE

RST 7.S TERMINATES THALT STATE

2-16

Image 39

$Intel MCS-80/85 manual J li\ Lr V V- U V u u u U, ~--r$

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.

Contents

Page Inter INTEl Corporation Table of Contents Page Introduction Page Chapter Part 1 Introduction to Functions of a Computer Instruction Register and Decoder Program Counter Jumps, Subroutines and the Stack Timing Control CircuitryAddress Registers Arithmetic/Logic Unit ALU Wait memory synchronization Instruction FetchMemory Read Memory Write Module Evolution MCS·SS Microcomputer System Introduction to MCS-85 Software Compatibility 8155 =CE, 8156 =CE MCS·S5 Special Peripheral Components ·1. MCS·SS Basic System Interfacing to MCS·80/8S Programmable Peripheral Components Programmable PeripheralsMEMil. lOR Demultiplexing the BUS Interfacing to Standard Memory Conclusions THROUGHPUT/COST Instruction CYCLE/ACCESS TimeSystem Performance Distributed ProcessingPage Functional Description Page Whatsin the 808SA ·1 808SA CPU Functional Block Diagram Hexadecimalbinary A7H Hexidecimal Binary AEH122H ·28085A Clock Logic ·38085A Hardware and SOFT· Ware RST Branch Locations ·5RIM Read Interrupt Mask ·4INTERRUPT Masks SET Using SIM Instruction Branched to When Inter· Rupt occursName Priority Type ·8BASIC CPU Functions HOW the MCS·85SYSTEM Works ·9 CPU Timing for Store Accumulator Direct STA Instruction Functional Description ·12808SA Machine State Chart ·13OPCODE Fetch Machine Cycle of DCX Instruction Lililili Memory Write MW Jl..Jl..Jl..J LIl..Jl..J ~ U- U-U V V U Lr \F LrLrU-U-U-U- U ~--r \J li\ Lr V V- U V u u u U ·21 Hold VS Interrupt NON Halt RST 7.5 Mask Resets SetsRST 5.5 Mask RST 6~5 Mask 7J==- 10ms.c = ~ ALE Signals Function AS-AI5 101M =x---C Conclusion Page System Operating Page Lhld MvimLOA STA Address Assignment System Operation To , , I X X X Memory·Mapped ·-·-1 Interfacing to MCS·80 Peripherals Interfacing to Standard BUS MemoriesDynamic RAM Interface ·3 MCS·80 Peripherals with 110 Mapped Parts Functions Minimum MCS-85 System T1t Scale =11 System Operation ·8 Expanded System CPU System Operation Expanded MCS·85 SystemParts Function ROM/EPROMPage Functional Description Page Chapter 8080 Central Processor Unit Registers Arithmetic and Logic Unit ALU Instruction Register and ControlData Bus Buffer Machine Cycle Identification State Transition Sequence Status Bit Definitions $ no Irr\ RL- rL- rL.-h rL-h -h rL-rL- r-L State Associated Activities LnLn IrL Hold Sequences ~ ~ ~~ w---t. ~~u----t Wl ~ ~ Page Page Page Page Condition Iiii Instruction Set Page 011 E 100 H H,LH,SP 000 B \JNN LabelInstruction and Data Formats Data Word Condition Flags Addressing Modes Instruction SET Encyclopedia O o 1 1 o Instruction SET Xchg ADD MP,CY,AC R CY ~-1 ~-· P,AC «H L8085, 5 DAA \ r00 0 S S S Address,jng Cleared RLC ORA M CMA CMC1 1 1 1 Condition «SP Cycles 2/5 8085,315 States 9/18 8085, 11/17 Pchl Flag WordPop 1 0 16 8085, 18 RIM NOP SIM 8085A 8080Al8085A Instruction SET Index Sossa 808SA 808SA Instruction SET Summary Contd Device Specifications Page Inter Inter Absolute Maximum RATINGS· LC~ Wait Inter 8080Al8080A·1/8080A·2 Waveforms Data and Instruction Formats Instruction Set Summary Inter8080Al8080A·118080A·2 Inter8080A/8080A·1/8080A·2 8085AH Pin AH CPU Functional Block Diagram Configuration 8085AH/8085AH-2/8085AH-1 Pin Description Interrupt Priority, Restart Address, and SensitivityVee Interrupt and Serial 1/0 Driving the X1 and X2 Inputs LC Tuned Circuit Clock Driver Quartz Crystal Clock DriverMHz Input Frequency External Clock Driver Circuit RiD~ 001 AH Basic System Timing AH Machine State Chart SOS5AH/SOS5AH-2/S0S5AH-1 Absolute Maximum RATINGS· 8085AH/8085AH-2/8085AH-1 Characteristics 8085AH 8085AH-2 8085AH-1 Bus Timing Specification as a Teye Dependent Symbol TlDW 8085AH/8085AH-2/8085AH-1 Waveforms IntJ 8085AH/8085AH-2/8085AH-1 I8085AH/8085AH-2/8085AH-1 SA Pin CPU Functional Block Diagram = ov ±5%, Vss = OV unless otherwise specified Absolute Maximum Ratings Xi Rising to ClK Falling 150 TCYC ClK Cycle Period 320 2000ClK low Time Standard ClK loading 120 Tnt ClK Rise and Fall Time TXKR Rising to ClK Rising Address TRD Read or Inta to Valid Data Symbol Parameter 8085A2 8085A·22 Units Min MaxReady Setup Time to leading Edge Trailing Edge of Read to Re·EnablingPage Appendix Page Appendix AP.PLICATIONS of MCS-85 Baud Rates MCS-85 Applications 111J RLm LlL R14 PAt8~~P Additional 808SA Interrupts As an example letslook at IntelsROM/EPROM family Fig 16K 32K64K Memory Addressing Ihl YT~~ Static Memories EJ EJ EJ DMA Direct Memory Access DataRefresh LXI Sp During initializationD5H A4H =11 System Timings OT~ ·2Clock Related Timing Vs MHz Considerations 2T-80 Minimum System Memory Device Compatibility BOSSA, A-2Memory Compatibility AddreS? access TAD MEM Chip select accessAddress access TAD MEM Chip select access Output enable TRD MEM Bus Compatibility Analysis see Figure Gates Ns ea Flip Flop Return path 2 8216s CAS path from ALE 41 ns TDHR 160 nsBus Compatibility Analysis see Contd Gates Flip Flops 15 ns 8216s 30 ns Flip flop 200 Schotiky or 1 Htil Input Current TIL single load 40p,A 6mA Schottky or Htil10p,A TIL + 36 MOS Application Example 333 1 D1 Software Temperature Sensor Flow Diagram ~.,.-~ Thermistor Resistance Mapping Clear HL Has the entireJNZ search Return CRT Interface RS·232C Interface Schematic Fi1 Output Routine PP-l POP !?HALFPrT + 6 = HOiHO = 01H Bf?E Cassette Recorder Interface One Chip Magnetic Tape Interface Schematic FeNO ButBLl2 T01 ~1V! A..OCeH Bf1 JC TIl Additional Comments A1·43 Temperature Sensor Code Temperature Sensor Code Contd Temperature Sensor Code Contd Temperature Sensor Code Contd CRT and Cassette Code Ep! l ?EceE81B BRm 08,.1 E87B C2760S 104 \/1ES77 C2760S 102 ES7A Le? SEce 06e93E01 TIl . Repeat Until Full BrTE ASSEt-18LEr 0911 C2OC99 9914 C9RERn Eight Opta ens TI2 089E BlnIN a ,38 Eurcd aTu30B €18F2 RRcr ErTINBITSr BtlPage Workshops Page Experience Intel Workshops SAN Francisco BAY Area Boston AreaChicago Area Dallas Area Lab sessions on SDK-8S System Design Kit Introduction to Microprocessors MCS-80/85 Microprocessors Domestic Sales Offices IntJ ~9Jf69rt,~~9 \.,1 Inter Service Offices