CRT and Cassette Code (Cont'd)

ISIS- II

80:313/8118'5 ASSEMBLER. '"'1

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PAGE

2

 

:?e85 SEPIAL i/O 1·10r.E APPHIOI >::

 

 

 

 

 

 

 

 

 

 

 

 

 

lOC

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SOIJRCE STATEMHlT

 

 

 

 

 

 

 

 

 

 

 

1

 

THE FOLLO~~ING P~O(JRA~lS At-ID SUBROUTINES ARE DESCRIBED IN DETAIL

 

2

.:

 

:..'

IN HITEL CORPERATIOWS

APPLICATION NOTE

AP-29,

"USING THE

a0S5

 

4 .:

SERlf'tI..

I/O

LINES".

THE

FIF.:Si

SECTION IS

A GENERIiL

PURPOSE

CRT

 

5 .

INTERFACE

tHTH

~UTt)MATIC

BAt!!)

RATE

WENTIFICATION.:

THE ~.ECOND

 

S .

~J:TTWN

IS

H MAGNETIC

TAPE INTERFACE FOR STORING OftTA ON CASSETTE

 

?

:

TAPES

THE CODE PRESENTED HERE IS ORIGINED AT LOCATION BOOH,

 

8

:

fmC! MIGHT 8E PART OF AN E::-~PANSION PP.O~l IN AN INTEL SDK-85

 

 

9 :

S'.'ST£M (:f.S IGN n T

 

 

 

 

 

 

 

 

 

 

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11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2OC8

E

BITTIt1E

Eo.lI

20C8H

: Af'ORESS OF SiORAfJE FOR COP1PUTEv BIT DELAY

 

2eCA

14

HAlFBIT EQlJ

23CAH

:ADDRESS OF STORAl3E

FOR HALF BIT

DELAY

 

aOOB

15 8ITSO

EO!J

11

 

.: ['ATABITS POT OI.lT (INCLUDING TWO STOP BITS)

....

 

0099

16 8ITS!

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9

 

.: DATA BITS TO BE RECIEVE[' (INCLUDING ONE STOP BID

 

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0see

18

 

ORG

~:eeH

.: STARTING AODRESS OF SCoK-S5 E:~PANSION PROI'l

 

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

213 .: eRTTST CPT HITEPFACE TEST. lHN CALLED, AWAITS THE SPACE BAR BEING PRESSED ON

 

21;

THE ';'r'STEt'l CONSOLE..

AND

THtN RESPONDS WITH Po [,ATA

R~TE YERIFICATION

 

22

:

~1ESSAGE

 

THERE

AFTER.

CHARt=!CTERS T'tPE(!ON THE KE'''SOARDARE ECHOED

 

21;

O~~ THE

£:tISPLP.Y

TUBE.

 

~iHEN A BREFW

KE'" IS WPED, THE I':OIJTHlE 15

24:Pf-STAPTED. AlLC~mlG A DIFFERENT BAtiE) RATE TO BE SELECTED ON THE CRT.

02.013

11C0213

2~

CRTT'::r·

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SP.. 28C:)H

.: 50(:0 MtlST BE HIGH BETWEal CHARACTERS

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27

 

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BRIO

.; WENTIF'r' DATA RATE USED B'"TERtlIHAL

98139

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29

 

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SrGNO~l

;OUTPUT ':IG~ION MESSAGE AT RATE OETEGTEL'

98ac

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:a 1=CI10'

CALI..

CHi: REAr) NE:':Tk:EYSTRorE

INTO REGISTER C

B:?eF

79

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~101/

8. ~:

 

~lAS A <:BREAIC' (ASCI I OOH)

13810

87

:2

 

ORA

A

.~ CHEer. IF CHARAI::TER

 

 

 

 

 

(RH

: rF 50. RE-IDENTIF't'

DATA RATE

 

 

 

 

 

 

.. TH I5 ALUJl.1S ~~jTHER RATE TO BE SELECTED ON CRT

13814

C[l6908

 

 

CALL

COUT

; OT4ERmSE COpy REGISTER C TO THE SCREEN

13817 cace8

36

 

.IMP

ECHO

.: CO~ITINUE IN[IEFINITEL'r' (UNTIL 8REAIO

 

 

~7

 

 

 

 

 

?-8.:BPWBAfJ[i RATE Ir.tEHTIFICATION SUBROUTTNE

1.9; E:~PECTS A '::CR) (Poser r 2i3l{:, TO E:E PECIEVEfi FRO/'! THE CONSOLE.

 

 

413;

THE LENGTH (f THE WITIAL ZERO LEVEL '.:51i<,

BITS tHDE) IS ~1EP'SIjREO

 

 

41

;

IN .ORDER TI) [lETEP~1INE THE DATA RRTE FOR FUTURE COMt1IJNICATIONS.

aS1A 29

42 BRIO'

PIt1

 

.: VEPIFY THAT

THE

"Ot-lE"

LEVEL HAS E'.EEN ESTflBLISHED

e81B 87

 

 

ORA

P-

: \ AS THE CRT

I S PO~lERLNG UP

ee1C F21Ae8

44

 

jp

BRm

 

 

 

 

 

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29

45

PoPIi

RIM

 

.; ~~JNnOR 5W LHIE

STATlIS

 

13829 B7

46

 

ORA

fi

 

 

 

 

 

13821

FMF0S

47

 

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.; LOOP UNTIL STA~:T

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15 RECIE'·/ED

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·48

 

U':I

H.. - 6: BIAS COUNTER

USED IN

[:t£TERtofINING ZERO [JURATION

13827

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13829

1(,

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ep!'l.

[:{R

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.: 51 MRCHINE C'r'CLE

DELAY LOOP

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eB2D

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w;':

H, m::RHlENT COUNTER EVER"

84 C'r'CLE5 WHILE SID IS l!lol

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RIM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1-49

Page 190
Image 190
Intel MCS-80/85 manual ?Ece, E81B, BRm, Ep! l, MRHlENT Counter Ever

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.