'-I"I,

I,

~'i,'

1'1

burst is being received when TAPEIN is called, wait until the burst is over:

TAPEIN: Mill B,8

~1\lI O..eeH

TI1: CflLl SiTIN

JC TIl

CALL SIiIN

JC Til

(Throughout this subroutine, a level transition is recognized only after it has been read once initially and then verified on the next reading. This pro- vides some degree of software noise immunity.) Now await the start of the next burst:

TI2 CFlLL BHIN

.TNC TI2

Ctill E:I,W

,me TI2

The next burst has now arrived. Keep reading the SID pin, decrementing register D (thus making it more negative), each cycle until the pause is detected:

T13 nCR [:t

CRLL 8iTIN

JC TIl

CRlL E:ITiH

JC H2

Now continue reading the SID pin, incrementing the D register (back towards zero), each cycle until the next burst is received:

TI4 rt-JR 0

(FILL SITYN

JNC TI4

CRll SHIN

JNC TI4

Now, if the burst lasted longer than the space, D was not incremented all the way back to zero; it is still negative. If the space was longer, D was incre- mented up through zero; it is now positive. In other words, the sign bit of D will now correspond to the data bit that would lead to each of these results. Move the sign bit into the CY, then rotate it into register C:

I'tIV ltD

~AL

MOV A,C

RAR

l1GV CA

Mill D,0l1r1

Continue until the last bit has been received:

[.oCR B

JNZ TI3

RET

(Notice that the first half of this subroutine is incorporated in the second half. In fact, the as- sembled listing included in the Appendix makes use of this fact to eliminate 24 bytes of duplicated code.)

BITIN waits a short time in order to regulate the sampling rate, then reads SID and moves the data bit into the CY:

BITW:

l'tVi

E, CI(RATE

(7"

 

 

 

I~

8I1:

OCR

E

(4)

 

JNZ

Bf1

(7/1iD

 

PIM

 

(4)

 

RAL

 

(4)

 

RET

 

<1.0>

The tone burst frequency and duration, and the TAPEIN sampling rate are determined by HALFCYC, CYCNO, and CKRATE. Tables 10 and 11 give typical values.

Table 10

EXAMPLE COMBINATIONS OF HALFCYC AND CYCNO.

ALL VALUES IN DECIMAL

APPROXIMATE

CORRESPONDING

 

RESULTING DATA RATE

TONE

HALFCYC

8

 

20

100

CYCNO

FREQUENCY

VALUE

4

 

10

50

CYC/BURST

 

 

 

 

 

 

 

500 Hz

217

42

 

17

3.3

bps

1 kHz

108

83

 

33

6.6

bps

2 kHz

53

166

 

66

13

bps

5 kHz

20

414

 

166

33

bps

10 kHz

9

826

 

330

66

bps

Table 11

MAXIMUM SAMPLING RATES

FOR VARIOUS VALUES OF

CKRATE

CKRATE

SAMPLING RATE

(INCLUDING

VALUE

CALL & RET)

 

 

 

 

1

17.6

J..lsec

20

104

J..lsec

80

378

J..lsec

250

1.14 msec

 

 

 

A1-41

Page 182
Image 182
Intel MCS-80/85 manual JC TIl, Bf1

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.