Intel MCS-80/85 manual TCYC ClK Cycle Period 320 2000, ClK low Time Standard ClK loading

inter 808SA/808SA-2

A.C. CHARACTERISTICS (TA = O°C to 70°C, Vee = ov ±5%, vss = OV)

						8085AI2J			12J
Symbol				Parameter				8085A·2		Units
						Min.	Max.	Min.	Max.
tCYC		ClK Cycle Period				320	2000	200	2000	ns
t1		ClK low Time (Standard ClK loading)				80		40		ns
t2 ..		ClK High Time (Standard ClK loading)				120		70		ns
tnt,		ClK Rise and Fall Time					30		30	ns
tXKR		X1 Rising to ClK Rising				30	120	30	100	ns
t yle!:		Xi Rising to ClK Falling				30	150	30	110	ns
t	AC	A _ Valid to leading Edge of Control l1			!	270		115		ns
		S	15
t ACL		AO-7 Valid to leading Edge of Control				240		115		ns
tAD		A -	15	Valid to Valid Data In			575		350	ns
		O
tAFR		Aaaress Float After leaalng Edge Of
		READ"ciNTA)					0		0	ns
tAL		AS-15Valid Before Trailing Edge of AlE[1]				115		50		ns
tALL		AO-7 Valid Before Trailing Edge of ALE				90		50		ns
tARy		READY valla from Aaaress valla					220		100	ns
tr.A		Aaaress (AS-15) valla After control				120		60		ns
tcc		Width of Control low (RD, WR, INTA)
		Edge of ALE				400		230		ns
tCl		Trailing Edge of Control to leading Edge				.
		of ALE				50		~		ns
tow		Data Valid to Trailing Edge of WRITE				420		230		ns
tHABE		HlDA to Bus Enable					210		150	ns
tHABF		Bus Float After HlDA					210		150	ns
t HACK		HlDA Valid to Trailing Edge of ClK				110		40		ns
tHDH		HOLD Hold Time				0		0		ns
t HDS		HOLD Setup Time to Trailing Edge of ClK				170		120		ns
tlNH		INTA HOla Time				0		0		ns
tINS		INTR, RS1, and TRAP Setup Time to
		Falling Edge of ClK				160		150		ns
tLA		Address Hold Time After ALE				100		50		ns
t LC		Trailing Edge of ALE to leading Edge
		of Control				130		60		ns
tLCK		ALE low During ClK High				100		50		ns
tLDR		ALE to valla Data During Read					460		270	ns
tLDW		ALE to Valid Data During write					200		120	ns
tLL		ALE Width				140		80		ns
t LRy		ALE to READY Stable					110		30	ns

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6-28 AFN-01242C