Intel MCS-80/85 manual Inter

inter			8080Al8080A·118080A·2
			Table 1. Pin Description
	Symbol	Type	Name and Function
	A1S;Ao	0	Address Bus: The address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O
			device number for up to 256 input and 256 output devices. Ao is the least significant address bit.
	DrDo	I/O	Data Bus: The data bus provides bi-directional communication betweeen the CPU, memory, and I/O
			devices for instructions and data transfers. Also, during the first clock cycle of each machine cycle, the
			8080A outputs a status word on the data bus that describes the current machine cycle. Do is the least
			significant bit.
	SYNC	0	Synchronizing Signal: The SYNC pin provides a signal to indicate the beginning of each machine cycle.
	DBIN	0	Data Bus In: The DBIN signal indicates to external circuits that the data bus is in the input mode. This
			signal should be used to enable the gating of data onto the 8080A data bus from memory or I/O.
	READY	I	Ready: The READY signal indicates to the 8080A that valid memory or input data is available on the 8080A
			data bus. This signal is used to synchronize the CPU with slower memory or I/O devices. If after sending
			an address out the 8080A does not receive a READY input, the 8080Awill enter a WAITstate for as long as
			the READY line is low. READY can also be used to single step the CPU.
	WAIT	0	Wait: The WAIT signal acknowledges that the CPU is in a WAIT state.
	WR	0	Write: The WR signal is used for memory WRITE or I/O output control. The data on the data bus is stable
			while the WR signal is active low (WR = 0).
	HOLD	I	Hold: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state allows an external
			device to gain control of the 8080A address and data bus as soon as the 8080A has completed its use of
			these busses for the current machine cycle. It is recognized under the following conditions:

•the CPU is in the HALT state.

•the CPU is in the T2 or TW state and the READY signal is active. As a result of entering the HOLD state the CPU ADDRESS BUS (A1S-Ao) and DATA BUS (D7-DO) will be in their high impedance state. The CPU acknowledges its state with the HOLD ACKNOWLEDGE (HLDA) pin.

HLDA	0	Hold Acknowledge: The HLDA Signal appears in response to the HOLD signal and indicates that the data
		and address bus will go to the high impedance state. The HLDA signal begins at:
		• T3 for READ memory or input.
		• The Clock Period following T3 for WRITE memory or OUTPUT operation.
		In either case, the HLDA signal appears after the rising edge of cP2.
INTE	0	Interrupt Enable: Indicates the content of the internal interrupt enable flip/flop. This flip/flop may be set
		or reset by the Enable and Disable Interrupt instructions and inhibits interrupts from being accepted by
		the CPU when it is reset. It is automatically reset (disabling further interrupts) at time T1 of the instruction
		fetch cycle (M1) when an interrupt is accepted and is also reset by the RESET signal.
INT	I	Interrupt Request: The CPU recognizes an interrupt request on this line at the end of the current
		instruction or while halted. If the CPU is in the HOLD state or if the Interrupt Enable flip/flop is reset it will
		not honor the request.
RESET1	I	Reset: While the RESETsignal is activated, the content of the program counter is cleared. After RESET,
		the program will start at location 0 in memory. The INTE and HLDA flip/flops are also reset. Note that the
		flags, accumulator, stack pOinter, and registers are not cleared.
Vss		Ground: Reference.
Voo		Power: +12 :+:5% Volts.
Vee		Power: +5 :+:5% Volts.
VSB		Power: -5 :+:5% Volts.
cP1, cP2		Clock Phases: 2 externally supplied clock phases. (non TTL compatible)

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