Intel MCS-80/85 manual Lr \F LrLrU-U-U-U- U

FUNCTIONAL DESCRIPTION

2.3.5Bus Idle (BI) and HALT State

Most machine cycles of the SOS5A are associated with either a READ or WRITE opera- tion. There are two exceptions to this rule. The first exception takes place during M2 and M3 of the DAD instruction. The SOS5A requires six in- ternal T states to execute a DAD instruciton, but it is not desirable to have M1 be ten (four normal plus six extra)·states long. Therefore, the CPU generates two extra machine cycles that do not access either the memory or the 1/0. These cycles are referred to as BUS IDLE (BI) machine cycles. In the case of DAD, they are identical to MR cycles except that RD remains high and ALE is not generated. Note that READY is ignored during M2 and M3 of DAD.

The other time when the BUS IDLE machine cy- cle occurs is during the internal opcode genera- tion for the RST or TRAP interrupts. Figure 2-19illustrates the BI cycle generated in response to RST 7.5. Since this interrupt is rising-edge- triggered, it sets an internal latch; that latch is sampled at the falling edge of the next to the last T-state of the previous instruction. At this pOint the CPU must generate its own internal RESTART instruction which will (in subsequent machine cycles) cause the processor to push the program counter on the stack and to vector to location 3CH. To do this, it executes an OF machine cycle without issuing RD, generating the RESTART opcode instead. After M1, the CPU continues execution normally in all respects except that the state of the READY line is ignored during the BI cycle.

SIGNALS		Ml I0F )				MllBII				M2 IMW )
	T3	T4	Tl	T2	T3	T4	T5	T6	Tl	T2

ClK	V\A:::.		Lr\FLrLrU-U-U-U-U
RST 7.5		>-~
									\.
101M					I
SI, so
			C					X
A8'A15	~			)(			PCH			ISP·l)H
	IPC·I)H
	IN					OUT				OUTIN

ADO·AD 7 ~~~--E)----- ------ --E K=:

ALE	1\		n
INTA
RD U
					L
WI!
READY	\	> ~		I

~

FIGURE 2·19RST 7.5 BUS IDLE MACHINE CYCLE

2-15