The 8085A'sCPU registers are distinguished as follows:

The accumulator (ACC or A Register) is the focus of all of the accumulator in- structions (Table 4-1), which include arithmetic, logic, load and store, and I/O instructions. It is an 8-bit register only, (However, see Flags, in this list.)

The program counter (PC) always points to the memory location of the next in- struction to be executed. It always con- tains a 16-bit address.

General-purpose registers BC, DE, and HL may be used as six 8-bit registers or as three 16-bit registers, interchangeably, depending on the instruction being per- formed. HL functions as a data pointer to reference memory addresses that are either the sources or the destinations in a number of instructions. A smaller number of instructions can use BC or DE for indirect addressing.

The stack pointer (SP) is a special data pointer that always points to the stack top (next available stack address). It is an indivisible 16-bit register.

The flag register contains five one-bit flags, each of which records processor status information and may also control processor operation. (See following paragraph.)

2.2.2Flags

. An addition operation that results in an overflow out of the high-order bit of the ac- cumulator sets the carry flag. An addition operation that does not result in an overflow clears the carry flag. (See 8080/8085 Assembly Language Programming Manual for further details.) The carry flag also acts as a "borrow" flag for subtract operations.

The auxiliary c~rry flag (AC) indicates overflow out of bit 3 of -the accumulator in the same way that the carry flag indicates overflow out of bit

7.This flag is commonly used in BCD (binary coded decimal) arithmetic.

The sign flag is set to the condition of the most significant bit of the accumulator following the execution of arithmetic or logic instructions. These instructions use bit 7 of data to represent the sign of the number contained in the ac- cumulator. This permits the manipulation of numbers in the range from -128 to + 127.

The zero flag is set if the result generated by certain instructions is zero. The zero flag is cleared if the result is not zero. A result that has a carry but has a zero answer byte in the ac- cumulator will set both the carry flag and the zero flag. For example,

HEXADECIMALBINARY

A7H

1010011 1

+59H

+01011001

100H

~1,0 0 0 0 0 000,

 

Carry bit I

 

Eight zero bits set zero flag to 1

The five flags in the 8085A CPU are shown below:

Incrementing or decrementing certain CPU registers with a zero result will also set the zero flag.

06

Is z

The parity flag (P) is set to 1 if the parity (number of 1-bits) of the accumulator is even. If odd, it is cleared.

2.2.3Stack

The carry flag (Cy) is set and reset by arithmetic operations. Its status can be directly tested by a program. For example, the addition of two one-byte numbers can produce an answer that does not fit into one byte:

HEXIDECIMAL

 

 

BINARY

 

 

 

AEH

1

0

1

0

1

1

1

0

+74H

o 1

1

1

0

1

0

0

122H

I1 0

0

1

0

0

0

1

0

.

Carry bit sets carry flag to 1.-

The stack pointer maintains the address of the last byte entered into the stack. The stack pointer can be initialized to use any portion of ~ead-writememory as a stack. The stack pointer IS decremented each time data is pushed onto the stack and is incremented each time data is popped off the stack (Le., the stack grows downward in terms of memory address, and the stack "top" is the lowest numerical address

represented in the stack currently in use). Note that the stack pointer is always incremented or decremented by two bytes since all stack

..~__~rations apply to register pairs.

........-............_-...-,.,

2-2

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Image 25
Intel MCS-80/85 manual Hexadecimalbinary A7H, Hexidecimal Binary AEH, 122H

MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.