THE INSTRUCTION SET

EI

(Enable interrupts)

 

The interrupt system is enabled following

the execution of the next instruction. Inter· rupts are not recognized during the EI instruction.

1 1 1

1 o 1 1

 

 

Cycles: 1

States: 4

Flags: none

NOTE: Placin~ EI instruction on the bus in response to INTA during an INA cycle is pro- hibited. (8085)

01(Disable interrupts)

The interrupt system is disabled immedi· ately following the execution of the 01 in· struction. Interrupts are not recognized during the 01 instruction.

1 1 1 1 o o 1 1

Cycles: 1

States: 4

Flags: none

NOTE: Placin~ 01 instruction on the bus in response to INTA during an INA cycle is pro- hibited. (8085)

HLT(Halt)

The processor is stopped. The registers and flags are unaffected. (8080) A second ALE is generated during the execution of HLT to strobe out the Halt cycle status in- formation. (8085)

o 11 o 1 o

Cycles: 1 + (~m85), 1 (8080)

States: 5 (8085), 7 (8080)

Flags: none

NOP

(No op)

No operation is performed. The registers and flags are unaffected.

o o o 0 o 0 o o

Cycles: 1

States: 4

Flags: none

RIM

(Read Interrupt Masks) (8085 only)

The RIM instruction loads data into the ac- cumulator relating to interrupts and the serial input. This data contains the follow- ing information:

•Current interrupt mask status for the RST 5.5, 6.5, and 7.5 hardware inter- rupts (1 = mask disabled)

•Current interrupt enable flag status (1

=interrupts enabled) except im- mediately following a TRAP interrupt. (See below.)

•Hardware interrupts pending (i.e., signal received but not yet serviced), on the RST 5.5,6.5, and 7.5 lines.

•Serial input data.

Immediately following a TRAP interrupt, the RIM instruction must be executed as a part of the service routine if you need to retrieve current interrupt status later. Bit 3 of the accumulator is (in this special case only) loaded with the interrupt enable (IE) flag status that existed prior to the TRAP interrupt. Following an RST 5.5,6.5, 7.5, or INTR interrupt, the interrupt flag flip-flop reflects the current interrupt enable status. Bit 6 of the accumulator (17.5) is loaded with the status of the RST 7.5 flip-flop, which is always set (edge-triggered) by an input on the RST 7.5 input line, even when that interrupt has been previously masked. (See SIM Instruction.)

7

 

 

 

 

 

 

 

0

 

I

Opcode:

 

I0

0

 

0

0

 

0

0

 

Accumulator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Content

 

 

 

 

 

 

 

 

 

 

After RIM:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Lnterru~tMasks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt Enable Flag

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupts Pending

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Input Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycles:

1

 

 

 

 

 

 

 

 

 

 

States:

4

 

 

 

 

 

 

 

 

 

 

Flags:

none

 

 

 

 

* All mnemonics copyrighted © Intel Corporation 1976.

5-17

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Intel MCS-80/85 manual Nop, Rim
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MCS-80/85 specifications

The Intel MCS-80/85 family, introduced in the late 1970s, is a seminal collection of microprocessors that played a pivotal role in the early days of computing. The MCS-80 series, initially targeting embedded systems and control applications, gained remarkable attention due to its innovative architecture and flexible programming capabilities.

The MCS-80 family is anchored by the 8080 microprocessor, which was one of the first fully integrated 8-bit microprocessors. Released in 1974, the 8080 operated at clock speeds ranging from 2 MHz to 3 MHz and featured a 16-bit address bus capable of addressing up to 64KB of memory. The processor’s instruction set included around 78 instructions, providing extensive capabilities for data manipulation, logic operations, and branching.

Complementing the 8080 was a suite of support chips, forming the MCS-80 platform. The most notable among them was the 8155, which integrated a static RAM, I/O ports, and a timer, tailored for ease of designing systems around the 8080. Other support chips included the 8085, which provided improvements with an integrated clock generator, making it compatible with more modern designs and applications.

The MCS-85 series, on the other hand, revolves around the 8085 microprocessor, which provided a more advanced architecture. The 8085 operated at clock speeds of up to 6 MHz and came with a 16-bit address bus, similar to its predecessor. However, it introduced more sophisticated features, including an enhanced instruction set and support for interrupt-driven programming. These enhancements made the 8085 especially appealing to developers working in real-time processing environments.

The MCS-80/85 family utilized NMOS technology, known for its lower power consumption and higher performance compared to previous technologies like TTL. The family’s architecture allowed for easy interfacing with a variety of peripherals, making it a favorite for educational institutions and hobbyists embarking on computer engineering projects.

With its robustness, versatility, and affordability, the Intel MCS-80/85 microprocessors laid the groundwork for many subsequent microcomputer systems and applications. The legacy of this powerful family continues to influence modern microprocessor design, emphasizing the importance of reliable architecture in a rapidly evolving technology landscape.
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