Chapter 3: Testing Performance
To test the multiple-clock state acquisition
have been configured with Falling Edge.
dClick OK to close the Analyzer Setup dialog.
9Verify the test data:
a Click the Run icon.
b If you have not already done so, do “Set up the Markers:” on page 34.
c If the "can't find 4096 occurence(s)" message does not appear, the test passes.
The test passes when the logic analyzer finds all occurances of the patterns programmed into the Markers. If the test passes, record a "Pass" in the performance test record under
10Test the next setup/hold combination: a Click the Bus/Signal Setup icon.
b Disconnect the clock just tested from the pulse generator.
c Repeat steps 1 through 10 for the next setup/hold combination listed in step 1 in page 52.
When aligning the data and clock waveforms using the oscilloscope, align the
waveforms according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.
Test the next channels (1680/81A, AD and 1690/91A, AD)
Connect the next combination of data channels and clock channels, then repeat the previous test.
Start with “Connect and configure the logic analyzer” on page 49, connect the next combination, then continue through the complete test.
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