Agilent Technologies 1680, 1690 manual 164

Page 164

Chapter 8: Theory of Operation

Agilent 1680A,AD-series Logic Analyzer Theory

resent via DMA transactions to an IEEE 1394 Link Layer chip. The Link Layer then transmits the data to a 1394 PHY (physical layer chip) where the data is transmitted over a 1394 cable to the motherboard for processing.

Test and Clock Synchronization Circuit. ECLinPS (ECL in pico seconds) ICs are used in the Test and Clock Synchronization Circuit for reliability and low channel-to-channel skew. Test patterns are generated and sent to the comparators during software operation verification (self-tests). The test patterns are propagated across all data and clock channels and read by the acquisition ICs to verify that the data and clock pipelines are operating correctly.

Clock and Data Threshold. The threshold circuit includes a precision octal DAC. Each of the eight channels of the DAC is individually programmable which allows the user to set the thresholds of the individual pods. The 16 data channels and the clock/data channel of each pod are all set to the same threshold voltage.

Motherboard Interface. The motherboard communications to the acquisition board over an IEEE 1394 interface residing on the acquisition board. Changes to the logic analyzer configuration made in application software are translated into configuration commands and then sent to the acquisition board through this interface. All state and timing functions including storage qualification, sequencing, assigning clocks and qualifiers, RUN and STOP, and thresholds are controlled in the manner.

A microcontroller manages initialization of the acquisition board at power-up, reconfiguring the acquisition board as a result of user input, and managing the IEEE 1394 communication to and from the motherboard.

A field programmable gate array (FPGA) bridges the 1394 interface to the rest of the acquisition board components. It also serves as the memory controller for the acquisition memory.

Memory Address Counters (MACs). Each acquisition IC has a CPLD that is used to provide addresses to the memory ICs that are written during an acquisition. The MACs are also used when uploading data to the GUI. Each CPLD contains three MACs. The MACs are configured serially by the FPGA prior to each acquisition and prior to each data upload. The application is responsible for setting up the proper address by writing to various register in the FPGA, which results in the MACs being serially programmed by the FPGA.

+5 VDC supply. The +5 VDC supply circuit supplies power to active logic analyzer accessories such as analysis probes. Thermistors on the +5 VDC supply lines protect the logic analyzer and the active accessory from overcurrent conditions. When an overcurrent condition is sensed, the thermistors create an open that shuts off the current rom the +5 VDC supply. After the overcurrent condition is resolved the thermistor closes the circuit and makes the supply current available.

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Contents Agilent Technologies 1680/90-Series Logic Analyzer Features Agilent 1680/90-Series Logic Analyzer-At a GlanceService Strategy This Book Contents To test the multiple-clock state acquisition Troubleshooting Theory of Operation General Information Accessories Accessories Supplied Agilent Part NumberSpecifications CharacteristicsFull Channel Channel CountProbes Dimensions Recommended Test Equipment Equipment RequiredPreparing for Use Power Requirements To inspect the logic analyzerTo apply power To connect the 1690A,AD-series logic analyzer to a host PCTo test the logic analyzer To clean the logic analyzerTo start the user interface Testing Performance Test Interval Qty To make the test connectorsMaterials Required Description To make the test connectors To set up the test equipment and the logic analyzer Set up the test equipmentEquipment Required Critical Specifications Pulse Generator Setup Timebase Channel TriggerChannel Define meas Set up the 1680A,AD-series logic analyzerOscilloscope Setup Acquisition Display Trigger Shift ∆ Time Set up the 1690A,AD-series logic analyzer To perform the logic analyzer self-testsSet the reporting level Click Close to close the Analysis System Self Tests dialog Set up the equipment To test the threshold accuracyConnect and configure the logic analyzer Test the ECL Threshold Test the 0 V User Threshold Test the next pod To set up the logic analyzer for the state mode tests To set up the logic analyzer for the state mode tests Click OK to close the Value dialog To set up the logic analyzer for the state mode tests To test the single-clock, single-edge, state acquisition Combinations Channel 2 Output Channel 1 OutputCombination Channel 2 Output Verify the test signal Check the setup/hold combination Setup/Hold Combinations Test Sample Position Times WindowTo test the single-clock, single-edge, state acquisition Following clock configurations will be used in steps 4, 5, To test the single-clock, single-edge, state acquisition Following clock configurations will be used in steps 9, 10 To test the single-clock, single-edge, state acquisition Test the next channels 1680/81A,AD and 1690/91A,AD To test the multiple-clock state acquisition 1680A, AD or 1690A, AD only 1682A, AD or 1692A, AD only Verify the test signal 2.0 ns 4.50 ns +3.0 ns To test the multiple-clock state acquisition To test the multiple-clock state acquisition Enable the pulse generator channel 1 Comp with the LED on Test the next channels 1680/81A, AD and 1690/91A, AD Modify the following pulse generator settings To test the single-clock, multiple-edge, state acquisition1680A,AD or 1690A,AD only Pod 2, channel 1682A,AD or 1692A,AD only Pod 1, channel Verify the test signal Check the setup/hold with single clock, multiple clock edges To test the single-clock, multiple-edge, state acquisition Following clock configurations will be used in steps 3, 4, To test the single-clock, multiple-edge, state acquisition Test the next channels 1680/81A,AD and 1690/91A,AD To test the time interval accuracy Function Generator Setup To test the time interval accuracy Acquire and verify the test data Click the Run icon to fill acquisition memoryTo test the time interval accuracy Test Settings Results Self-Tests Performance Test RecordThreshold AccuracyMultiple-Clock Multiple-Edge Acquisition Performance Test Record Settings ResultsEdge Acquisition Performance Test Record Settings Results Single-Clock Time IntervalPerformance Test Record Calibrating and Adjusting Logic analyzer calibration Troubleshooting To install the fan guard To use the flowcharts Troubleshooting the Agilent 1680A,AD-series StartReplace Power supply Are both instrument Yes Possible problem with LCD display, inverter, or cables Does the blue Uninstall, then reinstall Agilent Logic Analyzer application Possible problem with To check the power-up tests To test the power supply voltagesPower Supply Voltages Pin VoltageTo test the LCD display signals Equipment Required Critical Specification To test disk drive voltagesDisk Drive Voltages Pin No Signal Disk Drive Voltages Pin Signals Pin No To verify the CD-ROMTo recover the operating system To reinstall the operating systemProblems with the Operating System Troubleshooting the Agilent 1690A,AD-series Yes Is the power cord Connected? Consult host PC Test pass? To verify connectivity Task ManagerDevice Manager 100101 102 103 General TroubleshootingTo run the self-tests 104 105 Acquisition board status LEDs 106To test the logic analyzer probe cables 107108 109 To check the BNC Trigger input/output signals 110On the DC source, enter a voltage setting of 3.000 111To test the auxiliary power Digital Multimeter005% accuracy 112Replacing Assemblies 1131680A,AD-series disassembly/assembly Prepare the instrument for disassemblyTo remove the chassis from the sleeve 114To remove the acquisition board 115116 To remove the power supply 117To remove the hard disk drive 118To remove the CD-ROM drive assembly 119To remove the flexible disk drive 120121 To remove the PCI boards 122To remove the motherboard 123Transfer the I/O panel to the replacement board 124125 To remove the front panel assembly 126Reverse this procedure to install the front panel assembly 127To disassemble the front panel assembly 128To remove the distribution board 129To remove the inverter board 130To remove the fans 131To remove the cable tray 1321690A,AD-series disassembly/assembly 133To remove the fascia 134Remove the fascia away from the front panel 135136 To remove the deck 137138 139 To remove the line filter 140To remove the front panel and front frame 141142 Replaceable Parts 143Replaceable Parts Ordering 144145 Replaceable Parts ListSee Also Exploded View Agilent 1680A,AD-Series Replaceable Parts Replaceable Parts Ref. DesExchange Assemblies 1470515-0372 148149 150 Front Panel Assembly 151152 Exploded View Agilent 1690A,AD-Series Replaceable Parts 154155 156 Power Cables and Plug Configurations 157158 Plug Type Cable Plug Description Length Color Country In/cmTheory of Operation 159Agilent 1680A,AD-Series Logic Analyzer Block Diagram 160 Block-Level TheoryAgilent 1680A,AD-series Logic Analyzer Theory 161Power Supply Logic Acquisition Board Block DiagramAcquisition Board 162163 164 165 Power Distribution BoardFront Panel Board Agilent 1690A,AD-series Logic Analyzer Theory 166Power-up Self-Tests 1680A,AD-series Self-Tests DescriptionsConnectivity Tests 1690A,AD-series 167Acquisition Board Self Tests 168Logic Analyzer Self-Tests 169170 171 172 Manual Part Number Technology Licenses
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