Intel 21555 user manual 116

Page 116

I2O Support

and asserts p_inta_l to indicate to the host processor that one or more MFAs exist in the Outbound Post_List . Signal p_inta_l remains asserted until either the Outbound Post_List Counter is zero and the

outbound prefetch buffer empties, or the Outbound Post_List Mask bit is set.

The host processor removes the message from the Outbound Post_List by reading the 21555 CSR offset 44h. The 21555 maintains a 2 Dword outbound prefetch buffer to hold the next two MFAs from the Outbound Post_List. When this buffer is not empty and the Outbound Post_List Counter is non-zero, the 21555 returns TRDY# and the next MFA from its buffer. When the internal buffer empties as a result of this read operation, the 21555 automatically reads one or two more MFAs from the Outbound Post_List as described in the following paragraph.

When the 2 Dword buffer is empty, the 21555 treats a read to location 44h as a delayed memory read transaction. The address that the 21555 uses to initiate the transaction on the secondary bus is the current value of the Outbound Post_List Head Pointer. When the Outbound Post_List Counter is non-zero, the 21555 places the read request in a downstream delayed transaction queue entry reserved for fetching outbound MFAs as follows:

•When the Outbound Post_List Counter is 2 or higher, the 21555 performs a 2 Dword secondary bus memory read starting at the location addressed by the Outbound Post_List head pointer and places the read data in the 2 Dword buffer.

•When the Outbound Post_List Counter is 1, the 21555 performs a single Dword read.

When the read completes on the secondary bus, the 21555 decrements the Outbound Post_List Counter by 1 or 2, respectively. The 21555 increments the Outbound Post_List Head Pointer by either 1 or 2 Dwords, respectively, as well. When the initiator repeats the read of CSR location 44h, the 21555 returns the next MFA to the host.

When the Outbound Post_List Counter is zero and the prefetch buffer is empty, the 21555 immediately returns FFFFFFFFh to the host and does not enter the transaction in the delayed transaction queue and also does not decrement the Outbound Post_List Counter. When the counter decrements to zero and the 2 Dword prefetch buffer is empty, the 21555 deasserts p_inta_l, indicating that there are no more posted MFAs in the Outbound Queue.

Once the host processor consumes the outbound message from the local processor, it replaces the empty MFA onto the end of the Outbound Free_List. When the host processor replaces the empty MFA to the Outbound Free_List, it writes the Outbound Queue at the 21555 CSR offset 44h. The 21555 treats the write to location 44h as a posted write; that is, it returns TRDY# to the initiator and places the write data in the downstream posted write queue. The 21555 translates the address to the current value of the Outbound Free_List tail pointer. Once the empty MFA is queued in the posted write buffer, the 21555 increments the Outbound Free_List tail pointer. The 21555 can continue to accept writes to this address as long as there is room in the downstream posted write queue. The 21555 writes the data to the secondary bus location addressed by the Outbound Free_List tail pointer. When the write is completed, the 21555 increments the Outbound Free_List counter.

14.3Notes

•Read transactions to I2O Inbound and Outbound Queues at 40h and 44h are not ordered with respect to transactions in the posted write or delayed transaction queues. Reads to these two registers will not flush posted writes. Write transactions to these registers are placed in the posted write queue, and follow the same ordering rules as other posted memory writes.

•When the 21555 detects parity errors, a master abort or target abort during a read or write access to the Inbound or Outbound Queues, the 21555 treats the error condition the same way as it does any other delayed read or posted write.

•The 21555 queue pointers support FIFO sizes of 256, 512, 1K, 2K, 4K, 8K, 16K, and 32K entries. The number of entries is selectable in the Table 78, “Chip Control 1 Register” on page 160. The wrap function for all of the I2O pointers maintained by the 21555 is performed in hardware; therefore, all FIFOs must be located in an aligned address boundary.

116

21555 Non-Transparent PCI-to-PCI Bridge User Manual

Page 115 Page 117
Image 116
Page 115 Page 117
Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Figures Tables131 148 108 Page Brief description of the contents of this manual follows PrefaceTerm Words Bytes Bits Data UnitsNumbering Signal Nomenclature Signal Type AbbreviationsSignal Description Type STSRegister Abbreviations Access Type DescriptionRegister Abbreviations Introduction Comparing a 21555 to a Transparent PPBCPU PCI Dram PCI ROMCPU PPB Feature Comparison FeatureArchitectural Overview Data BuffersRegisters Control LogicMicroarchitecture Special Applications Programming NotesPrimary Bus VGA Support Secondary Bus VGA SupportROM Access Transaction ForwardingPage Group by Signal Pin Description See Signal DescriptionsSignal Pin Functional Groups Signal Name Type Description Primary PCI Bus Interface SignalsPrimary PCI Bus Interface Signals Sheet 1 Primary PCI Bus Interface Signals Sheet 2 PparPreql PstoplPrimary PCI Bus Interface 64-Bit Extension Signals Primary PCI Bus Interface 64-Bit Extension Signals Sheet 1Pack64l Pad6332Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2 Ppar64Preq64l Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Secondary PCI Bus Interface Signals Sheet 1Secondary PCI Bus Interface Signals Sheet 2 SparSstopl StrdylSecondary PCI Bus Interface 64-Bit Extension Signals Sack64lSad6332 Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Memory 0 Transaction Address Decoding CSR Address DecodingExpansion ROM Address Mapping Decoding Using the BAR Setup Registers BAR Setup Register ExampleDirect Address Translation Address FormatLookup Table Based Address Translation Direct Offset Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Lookup Table Entry Format Upstream Lookup Table Address TranslationForwarding of 64-Bit Address Memory Transactions Lookup Table Entry FormatI/O Transaction Address Decoding Indirect I/O Transaction GenerationAddress Decoding Subtractive Decoding of I/O Transactions Configuration AccessesType 0 Accesses to 21555 Configuration Space Initiation of Configuration Transactions by Address Decoding Bar Size Address Translation 21555 Bar SummaryBar Summary Page PCI Bus Transactions Transactions OverviewPosted Write Transactions Memory Write Transactions Memory Write and Invalidate TransactionsWrite Performance Tuning Options 3 64-bit Extension Posted Write TransactionWrite-Through Delayed Write Transactions Target Bus Response Initiator Bus Response Delayed Read TransactionsDelayed Write Transaction Target Termination Returns Delayed Read Transaction Target Termination Returns Nonprefetchable ReadsPrefetchable Reads Prefetchable Read Transactions Using the 64-bit ExtensionRead Performance Features and Tuning Options Prefetching Prefetch BoundariesRead Queue Full Threshold Tuning 64-Bit and 32-Bit Transactions Initiated byTarget Terminations Target Terminations Returned byTransaction Termination Errors on the Target Bus Ordering RulesTransaction Ordering Rules PCI Bus Transactions Page Initialization Requirements Power Management, Hot-Swap, and Reset SignalsPower Management, Hot-Swap, and Reset Signals Sheet 1 Reset Behavior Power Management, Hot-Swap, and Reset Signals Sheet 2Spmel SrstinlReset Mechanisms PrstlCentral Function During Reset 21555 InitializationWith SROM, Local, and Host Processors Without Serial PreloadPower Management Support Without Local ProcessorWithout Local Processor and Serial Preload Without Host ProcessorTransitions Between Power Management States Power Management ActionsNext Power State Action 2 PME# SupportOverview of CompactPCI Controller Hardware Interface Power Management Data RegisterCompactPCI Hot-Swap Functionality Primary Lstat K Ω Insertion and Removal ProcessPrstl 332 Ω Initialization Requirements W Disconnected W Connected2a INS ENUM# 4b InsertionInitialization Requirements Primary and Secondary PCI Bus Clock Signals Primary and Secondary PCI Bus Clock Signals Sheet 1Signal Name Description ClockingPrimary and Secondary PCI Bus Clock Signals Sheet 2 21555 Secondary Clock OutputsSclk Sclko66 MHz Support Page Interface Signals Parallel ROM InterfaceProm Interface Signals Sheet 1 Signal Type Description NameProm Interface Signals Sheet 2 Prom Read by CSR Access Parallel and Serial ROM Connection21555 WE# OE#Prom Read Timing Prom Write by CSR Access Prom Dword Read Prom Write TimingAccess Time and Strobe Control Read and Write Strobe TimingAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Srom Interface Signals Srom Interface SignalsSerial ROM Interface Sromsrom Preload OperationSrom Configuration Data Preload Format Srom Operation by CSR AccessSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Primary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterPrimary PCI Bus Arbitration Secondary Arbiter Example Bit Name Description Secondary Bus Arbitration Using an External ArbiterArbiter Control Register Primary and Secondary PCI Bus Interrupt Signals Primary and Secondary PCI Bus Interrupt SignalsInterrupt and Scratchpad Registers Interrupt SupportInterrupt and Scratchpad Registers Doorbell Interrupts Scratchpad RegistersPage Error Handling Error SignalsPrimary PCI Bus Error Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Type PER † Action Taken Error Transaction Parity ErrorsParity Error Responses Sheet 1 Asserts pperrl Parity Error Responses Sheet 2Error Transaction Parity Error Responses Sheet 3 Asserts sperrlSystem Error SERR# Reporting Jtag Test Port Jtag SignalsJtag Signals Test Access Port Controller InitializationI2O Support Inbound Message PassingI2O Support Outbound Message Passing 116 117 Page VPD Support Reading VPD InformationWriting VPD Information List of Registers Register SummaryRegister Cross Reference Table Theory of Operation Chapter Register Reference InformationConfiguration Registers Configuration Space Address Register Sheet 1Byte Reset Value Write Read Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Configuration Space Address Register Sheet 5 Register Name Reset Value Write Access Read AccessControl and Status Registers CSR Address Map Sheet 1CSR Address Map Sheet 2 Ffff W1TC CSR Address Map Sheet 3Ffff W1TS CSR Address Map Sheet 4 Address Decoding Primary and Secondary AddressCSR Address Map Sheet 5 Primary CSR and Downstream Memory 0 Bara Sheet 1Primary CSR and Downstream Memory 0 Bara Sheet 2 Secondary CSR Memory BARsa Sheet 1Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Secondary CSR Memory BARsa Sheet 2Primary and Secondary CSR I/O Barsa Upstream I/O or Memory 0 BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAROffsets Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upper 32 Bits Downstream Memory 3 Bar Upstream Memory 2 BarXlatbase Offsets Downstream I/O or MemoryTranslated Base Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Configuration Transaction Generation Registers Upper 32 Bits Downstream Memory 3 Setup RegisterDownstream and Upstream Configuration Address Registers CfgaddrConfiguration Own Bits Register CfgdataConfiguration CSR Sheet 1 Configuration CSR Sheet 2 Downstream I/O Address and Upstream I/O Address RegistersOffset Downstream I/O Address Upstream I/O Address Ioaddr IADownstream I/O Data and Upstream I/O Data Registers O Own Bits RegistersOffsets Downstream I/O Data Upstream I/O Data IodataLutoffset O CSRLookup Table Offset Register Configuration Registers PCI RegistersLookup Table Data Register Upstream Memory 2 Lookup TablePrimary Interface Configuration Space Address Map Secondary Interface Configuration Space Address MapVendor ID Register Device ID RegisterOffsets Primary Command Secondary Command Primary and Secondary Command RegistersPrimary and Secondary Command Registers Sheet 1 Primary and Secondary Command Registers Sheet 2 Primary and Secondary Status Registers Sheet 1SERR# Offsets Primary Status Secondary StatusPrimary and Secondary Status Registers Sheet 2 Revision ID Rev ID RegisterPrimary and Secondary Class Code Registers Primary and Secondary Cache Line Size RegistersOffsets Primary Class Code Secondary Class Code Offsets Primary Cache Line Size Secondary Cache Line SizeOffsets Primary MLT Secondary MLT Header Type RegisterBiST Register Subsystem Vendor ID Register Subsystem ID RegisterEnhanced Capabilities Pointer Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Maximum Latency Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Minimum Grant Registers Chip Control 0 Register Sheet 1 Device-Specific Control and Status RegistersDevice-Specific Control and Status Address Map Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 I20ENA Chip Control 1 Register Sheet 3Chip Status Register 163 Generic Own Bits Register Rots16.6 I2O Registers I2O Outbound PostList StatusI2O Outbound PostList Interrupt Mask I2O Inbound PostList StatusI2O Inbound PostList Interrupt Mask I2O Inbound QueueI2O Outbound Queue I2OOUT PI2O Inbound FreeList Head Pointer I2O Inbound PostList Tail PointerI2O Outbound FreeList Tail Pointer I2O Outbound PostList Head PointerI2O Inbound PostList Counter I2O Inbound FreeList CounterLdipc W1TLS Ldifc W1TLSLdopc W1TLS I2O Outbound PostList CounterI2O Outbound FreeList Counter Interrupt Registers Chip Status CSRChip Set IRQ Mask Register PMD0 W1TCPAGE0IRQ W1TC Chip Clear IRQ Mask RegisterUpstream Page Boundary IRQ 0 Register Upstream Page Boundary IRQ Mask 1 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 0 Register Primary Clear IRQ and Secondary Clear IRQ Registers Primary Set IRQ and Secondary Set IRQ RegistersPrimary Clear IRQ Secondary Clear IRQ Primary Set IRQPrimary Set IRQ Mask and Secondary Set IRQ Mask Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 1Primary Clear IRQ Mask Secondary Clear IRQ Mask Secondary Set IRQ MaskPrimary Expansion ROM BAR Prom RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 2 Primary Expansion ROM Setup Register Sequence onRomdata ROM Setup RegisterROM Data Register Romaddr ROM Address RegisterROM Control Register Sheet 1 Mode Setting Configuration Register Sheet 1 Srom RegistersROM Control Register Sheet 2 SrompollByte Description Offset Mode Setting Configuration Register Sheet 2Serial Preload Sequence Sheet 1 Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Error Registers Arbiter ControlPrimary SERR# Disable Register Secondary SERR# Disable RegisterPM ECP ID Power Management ECP ID and Next Pointer RegisterInit Registers Power Management Capabilities Register APSDSI PMEPower Management Control and Status Register Pmcsr Bridge Support ExtensionsPower Management Data Register Reset Control RegisterCompactPCI Hot-Swap Control Register Sheet 1 HS Next PointerJtag Instruction Register Options Sheet 1 Jtag RegistersCompactPCI Hot-Swap Control Register Sheet 2 Jtag Instruction Register Options Sheet 2 Bypass RegisterBoundary-Scan Register Boundary Scan OrderVPD ECP VPD RegistersVital Product Data VPD ECP ID and Next Pointer Register Vital Product Data VPD Address Register VPD Data RegisterPage Acronyms Acronyms Index CSR140
Related manuals
Manual 26 pages 60.05 Kb

21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
Top Page Image Contents