Intel 21555 Reset Behavior, Power Management, Hot-Swap, and Reset Signals Sheet 2, Spmel, Srstinl

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Initialization Requirements

Table 17. Power Management, Hot-Swap, and Reset Signals (Sheet 2 of 2)

Signal Name

Type

Description

 

 

 

 

 

Secondary bus power management event. The subsystem asserts this signal to the

 

 

21555 to indicate that it is signaling a power management event. The 21555

 

 

conditionally asserts p_pme_l when s_pme_l is asserted low.

s_pme_l

I

When the subsystem does not generate power management events, this signal can

 

 

also be used for a subsystem status signal. A deasserting (rising) edge on this signal

 

 

can conditionally cause the 21555 to assert p_inta_l.

 

 

When this signal is not used, it should be tied high with a 1k resistor.

 

 

 

 

 

Alternate reset input for the 21555. Asserting s_rst_in_l is the same as asserting

s_rst_in_l

I

p_rst_l. These two signals are ORed on the 21555. All configuration modes are

captured on this edge. Signal s_rst_in_l allows for either a reset to be initiated from

 

 

 

 

the secondary bus or a board reset for a hot-swap.

Secondary PCI bus RST#. Signal s_rst_l is driven by the 21555 and acts as the PCI reset for the secondary bus. The 21555 asserts s_rst_l when any of the following conditions are met:

 

 

•

Signal p_rst_l is asserted.

 

 

• The secondary reset bit in the Table 123, “Reset Control Register” on page 188 in

 

 

 

configuration space is set.

 

 

• The chip reset bit in the Table 123, “Reset Control Register” on page 188 in

 

 

 

configuration space is set.

s_rst_l

O

•

Power management transition from D3hot to D0 occurs.

 

 

When the 21555 asserts s_rst_l, it tristates all secondary control signals and, when

 

 

designated as the secondary bus central resource, asserts s_req64_l and drives

 

 

zeros on s_ad, s_cbe_l, and s_par.

 

 

Signal s_rst_l remains asserted until p_rst_l is deasserted, and the secondary reset

 

 

bit is clear. Deassertion of s_rst_l occurs automatically based on internal timers when

 

 

s_rst_l assertion is caused by setting the chip reset bit or a power management

 

 

transition.

 

 

Assertion of s_rst_l by itself does not clear register state, and configuration registers

 

 

are still accessible from the primary PCI interface.

6.2Reset Behavior

The 21555 implements a primary reset input, p_rst_l, a secondary reset input s_rst_in_l, and a secondary reset output, s_rst_l. The 21555 also implements a Chip Reset bit and a Secondary Reset bit in the Table 123, “Reset Control Register” on page 188.

The device is reset when one of the following occurs:

•The signal p_rst_l is asserted.

•The signal s_rst_in_l is asserted.

•The Chip Reset bit is written with a 1.

•A power management transition from D3hot to D0 occurs (see Section 6.4.1).

When the Chip Reset bit is written with a 1, the chip reset bit is cleared 7 clocks after it is set. The actual chip reset signal is internally delayed to allow the configuration cycle to complete normally. Chip reset causes all the register values to be reset, and all the queues to be cleared. The primary PCI bus and control signals are tristated as long as either chip reset is occurring or p_rst_l is asserted.

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21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Figures Tables131 148 108 Page Brief description of the contents of this manual follows PrefaceData Units NumberingTerm Words Bytes Bits Signal Description Type Signal NomenclatureSignal Type Abbreviations STSAccess Type Description Register AbbreviationsRegister Abbreviations Introduction Comparing a 21555 to a Transparent PPBDram PCI ROM CPUCPU PCI PPB Feature Comparison FeatureRegisters Architectural OverviewData Buffers Control LogicMicroarchitecture Primary Bus VGA Support Special ApplicationsProgramming Notes Secondary Bus VGA SupportROM Access Transaction ForwardingPage Signal Descriptions Signal Pin Functional GroupsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Primary PCI Bus Interface Signals Sheet 1Signal Name Type Description Preql Primary PCI Bus Interface Signals Sheet 2Ppar PstoplPack64l Primary PCI Bus Interface 64-Bit Extension SignalsPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Pad6332Preq64l Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Ppar64 Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Secondary PCI Bus Interface Signals Sheet 1Sstopl Secondary PCI Bus Interface Signals Sheet 2Spar StrdylSad6332 Secondary PCI Bus Interface 64-Bit Extension SignalsSack64l Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding CSR Address Decoding Expansion ROM Address Mapping DecodingMemory 0 Transaction Address Decoding Using the BAR Setup Registers BAR Setup Register ExampleDirect Address Translation Address FormatLookup Table Based Address Translation Direct Offset Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Lookup Table Entry Format Upstream Lookup Table Address TranslationForwarding of 64-Bit Address Memory Transactions Lookup Table Entry FormatI/O Transaction Address Decoding Indirect I/O Transaction GenerationAddress Decoding Configuration Accesses Type 0 Accesses to 21555 Configuration SpaceSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding 21555 Bar Summary Bar SummaryBar Size Address Translation Page PCI Bus Transactions Transactions OverviewPosted Write Transactions Memory Write Transactions Memory Write and Invalidate TransactionsWrite Performance Tuning Options 3 64-bit Extension Posted Write TransactionWrite-Through Delayed Write Transactions Delayed Read Transactions Delayed Write Transaction Target Termination ReturnsTarget Bus Response Initiator Bus Response Delayed Read Transaction Target Termination Returns Nonprefetchable ReadsPrefetchable Read Transactions Using the 64-bit Extension Read Performance Features and Tuning OptionsPrefetchable Reads Prefetching Prefetch BoundariesRead Queue Full Threshold Tuning 64-Bit and 32-Bit Transactions Initiated byTarget Terminations Target Terminations Returned byTransaction Termination Errors on the Target Bus Ordering RulesTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Power Management, Hot-Swap, and Reset Signals Sheet 1Initialization Requirements Spmel Reset BehaviorPower Management, Hot-Swap, and Reset Signals Sheet 2 SrstinlReset Mechanisms PrstlCentral Function During Reset 21555 InitializationWith SROM, Local, and Host Processors Without Serial PreloadWithout Local Processor and Serial Preload Power Management SupportWithout Local Processor Without Host ProcessorNext Power State Action Transitions Between Power Management StatesPower Management Actions 2 PME# SupportPower Management Data Register CompactPCI Hot-Swap FunctionalityOverview of CompactPCI Controller Hardware Interface Insertion and Removal Process Prstl 332 ΩPrimary Lstat K Ω Initialization Requirements 2a INS ENUM# W DisconnectedW Connected 4b InsertionInitialization Requirements Signal Name Description Primary and Secondary PCI Bus Clock SignalsPrimary and Secondary PCI Bus Clock Signals Sheet 1 ClockingSclk Primary and Secondary PCI Bus Clock Signals Sheet 221555 Secondary Clock Outputs Sclko66 MHz Support Page Interface Signals Parallel ROM InterfaceProm Interface Signals Sheet 1 Signal Type Description NameProm Interface Signals Sheet 2 21555 Prom Read by CSR AccessParallel and Serial ROM Connection WE# OE#Prom Read Timing Prom Write by CSR Access Prom Dword Read Prom Write TimingAccess Time and Strobe Control Read and Write Strobe TimingAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Serial ROM Interface Srom Interface SignalsSrom Interface Signals Sromsrom Preload OperationSrom Configuration Data Preload Format Srom Operation by CSR AccessSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Primary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsSecondary Bus Arbitration Using the Internal Arbiter Primary PCI Bus ArbitrationSecondary PCI Bus Arbitration Secondary Arbiter Example Secondary Bus Arbitration Using an External Arbiter Arbiter Control RegisterBit Name Description Interrupt and Scratchpad Registers Primary and Secondary PCI Bus Interrupt SignalsPrimary and Secondary PCI Bus Interrupt Signals Interrupt SupportInterrupt and Scratchpad Registers Doorbell Interrupts Scratchpad RegistersPage Primary PCI Bus Error Signals Error HandlingError Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Errors Parity Error Responses Sheet 1Type PER † Action Taken Error Transaction Parity Error Responses Sheet 2 Error TransactionAsserts pperrl Parity Error Responses Sheet 3 Asserts sperrlSystem Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Test Access Port Controller InitializationI2O Support Inbound Message PassingI2O Support Outbound Message Passing 116 117 Page VPD Support Reading VPD InformationWriting VPD Information Register Cross Reference Table List of RegistersRegister Summary Theory of Operation Chapter Register Reference InformationByte Reset Value Write Read Configuration RegistersConfiguration Space Address Register Sheet 1 Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Control and Status Registers Configuration Space Address Register Sheet 5Register Name Reset Value Write Access Read Access CSR Address Map Sheet 1CSR Address Map Sheet 2 CSR Address Map Sheet 3 Ffff W1TSFfff W1TC CSR Address Map Sheet 4 CSR Address Map Sheet 5 Address DecodingPrimary and Secondary Address Primary CSR and Downstream Memory 0 Bara Sheet 1Primary CSR and Downstream Memory 0 Bara Sheet 2 Secondary CSR Memory BARsa Sheet 1Secondary CSR Memory BARsa Sheet 2 Primary and Secondary CSR I/O BarsaOffsets Primary CSR I/O BAR Secondary CSR I/O BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR OffsetsUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upper 32 Bits Downstream Memory 3 Bar Upstream Memory 2 BarOffsets Downstream I/O or Memory Translated BaseXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Configuration Transaction Generation Registers Upper 32 Bits Downstream Memory 3 Setup RegisterDownstream and Upstream Configuration Address Registers CfgaddrConfiguration Own Bits Register CfgdataConfiguration CSR Sheet 1 Offset Downstream I/O Address Upstream I/O Address Configuration CSR Sheet 2Downstream I/O Address and Upstream I/O Address Registers Ioaddr IAOffsets Downstream I/O Data Upstream I/O Data Downstream I/O Data and Upstream I/O Data RegistersO Own Bits Registers IodataO CSR Lookup Table Offset RegisterLutoffset Lookup Table Data Register Configuration RegistersPCI Registers Upstream Memory 2 Lookup TableVendor ID Register Primary Interface Configuration Space Address MapSecondary Interface Configuration Space Address Map Device ID RegisterPrimary and Secondary Command Registers Primary and Secondary Command Registers Sheet 1Offsets Primary Command Secondary Command SERR# Primary and Secondary Command Registers Sheet 2Primary and Secondary Status Registers Sheet 1 Offsets Primary Status Secondary StatusPrimary and Secondary Status Registers Sheet 2 Revision ID Rev ID RegisterOffsets Primary Class Code Secondary Class Code Primary and Secondary Class Code RegistersPrimary and Secondary Cache Line Size Registers Offsets Primary Cache Line Size Secondary Cache Line SizeHeader Type Register BiST RegisterOffsets Primary MLT Secondary MLT Enhanced Capabilities Pointer Register Subsystem Vendor ID RegisterSubsystem ID Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Interrupt Pin Registers Primary and Secondary Minimum Grant RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Registers Device-Specific Control and Status Address MapChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Control 1 Register Sheet 3 Chip Status RegisterI20ENA 163 Generic Own Bits Register RotsI2O Outbound PostList Interrupt Mask 16.6 I2O RegistersI2O Outbound PostList Status I2O Inbound PostList StatusI2O Outbound Queue I2O Inbound PostList Interrupt MaskI2O Inbound Queue I2OOUT PI2O Outbound FreeList Tail Pointer I2O Inbound FreeList Head PointerI2O Inbound PostList Tail Pointer I2O Outbound PostList Head PointerLdipc W1TLS I2O Inbound PostList CounterI2O Inbound FreeList Counter Ldifc W1TLSI2O Outbound PostList Counter I2O Outbound FreeList CounterLdopc W1TLS Chip Set IRQ Mask Register Interrupt RegistersChip Status CSR PMD0 W1TCChip Clear IRQ Mask Register Upstream Page Boundary IRQ 0 RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ 1 Register Upstream Page Boundary IRQ Mask 0 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Clear IRQ Secondary Clear IRQ Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Set IRQ and Secondary Set IRQ Registers Primary Set IRQPrimary Clear IRQ Mask Secondary Clear IRQ Mask Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Secondary Set IRQ MaskProm Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 2Primary Expansion ROM BAR Primary Expansion ROM Setup Register Sequence onROM Setup Register ROM Data RegisterRomdata ROM Address Register ROM Control Register Sheet 1Romaddr ROM Control Register Sheet 2 Mode Setting Configuration Register Sheet 1Srom Registers SrompollMode Setting Configuration Register Sheet 2 Serial Preload Sequence Sheet 1Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Error Registers Arbiter ControlPrimary SERR# Disable Register Secondary SERR# Disable RegisterPower Management ECP ID and Next Pointer Register Init RegistersPM ECP ID DSI Power Management Capabilities RegisterAPS PMEPower Management Control and Status Register Pmcsr Bridge Support ExtensionsPower Management Data Register Reset Control RegisterCompactPCI Hot-Swap Control Register Sheet 1 HS Next PointerJtag Registers CompactPCI Hot-Swap Control Register Sheet 2Jtag Instruction Register Options Sheet 1 Boundary-Scan Register Jtag Instruction Register Options Sheet 2Bypass Register Boundary Scan OrderVPD Registers Vital Product Data VPD ECP ID and Next Pointer RegisterVPD ECP Vital Product Data VPD Address Register VPD Data RegisterPage Acronyms Acronyms Index CSR140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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