Intel 21555 Device-Specific Control and Status Registers, Chip Control 0 Register Sheet 1

Page 156

List of Registers

16.5.3Device-Specific Control and Status Registers

This section contains information about the device-specific control and status registers.

Table 76. Device-Specific Control and Status Address Map

Byte 3

 

Byte 2

Byte 1

 

Byte 0

Primary

Secondary

 

 

Offset

Offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Control 1

 

Chip Control 0

CCh

CCh

 

 

 

 

 

 

 

 

 

 

 

Chip Status

D0h

D0h

 

 

 

 

 

 

 

 

Table 77. Chip Control 0 Register (Sheet 1 of 4)

This register may be preloaded by serial ROM or programmed by the local processor before host configuration.

•Primary byte offset: CD:CCh

•Secondary byte offset: CD:CCh

Bit

Name

R/W

Description

 

 

 

 

 

 

 

Controls the 21555’s behavior on the initiator bus when a master abort

 

 

 

termination occurs in response to a delayed transaction initiated by the

 

 

 

21555 on the target bus.

 

 

 

• When 0, the 21555 asserts TRDY# in response to a delayed

0

Master Abort

R/W

transaction, and returns FFFFFFFFh if a read. For posted writes,

Mode

SERR is not asserted on the initiator bus.

 

 

 

 

 

• When 1, the 21555 returns a target abort in response to a delayed

 

 

 

transaction. For posted writes, SERR will be asserted (if otherwise

 

 

 

enabled) on the initiator bus.

 

 

 

• Reset value is 0

 

 

 

 

 

 

 

Controls the disconnect boundary for memory writes. This bit does not

 

 

 

apply to MWI commands.

 

Memory Write

 

• When 0, the 21555 disconnects memory writes either on an aligned 4

 

 

KB boundary, a page boundary less than 4 KB (Upstream Memory

1

Disconnect

R/W

Range 2 only) or when the posted write queue is full.

 

Control

 

 

 

• When 1, the 21555 disconnects memory write on an aligned cache

 

 

 

 

 

 

line boundary, or when the posted write queue is full.

 

 

 

• Reset value is 0

 

 

 

 

 

 

 

Sets the maximum number of PCI clock cycles that the 21555 waits for an

 

 

 

initiator on the primary bus to repeat a delayed transaction request. The

 

 

 

counter starts when the delayed transaction completion is ready to be

 

 

 

returned to the initiator. When the initiator has not repeated the transaction

 

Primary

 

at least once before the counter expires, the 21555 discards the delayed

 

 

transaction from its queues.

2

Master

R/W

• When 0, the primary master timeout counter is 215 PCI clock cycles, or

 

Timeout

 

 

 

 

0.983 ms for a 33-MHz bus.

 

 

 

• When 1, the value is 210 PCI clock cycles, or 30.7 ∝ s for a 33-MHz

 

 

 

bus.

 

 

 

• Reset value is 0

 

 

 

 

156

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Figures Tables131 148 108 Page Brief description of the contents of this manual follows PrefaceData Units NumberingTerm Words Bytes Bits Signal Nomenclature Signal Type AbbreviationsSignal Description Type STSAccess Type Description Register AbbreviationsRegister Abbreviations Introduction Comparing a 21555 to a Transparent PPBDram PCI ROM CPUCPU PCI PPB Feature Comparison FeatureArchitectural Overview Data BuffersRegisters Control LogicMicroarchitecture Special Applications Programming NotesPrimary Bus VGA Support Secondary Bus VGA SupportROM Access Transaction ForwardingPage Signal Descriptions Signal Pin Functional GroupsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Primary PCI Bus Interface Signals Sheet 1Signal Name Type Description Primary PCI Bus Interface Signals Sheet 2 PparPreql PstoplPrimary PCI Bus Interface 64-Bit Extension Signals Primary PCI Bus Interface 64-Bit Extension Signals Sheet 1Pack64l Pad6332Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2 Ppar64Preq64l Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Secondary PCI Bus Interface Signals Sheet 1Secondary PCI Bus Interface Signals Sheet 2 SparSstopl StrdylSecondary PCI Bus Interface 64-Bit Extension Signals Sack64lSad6332 Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding CSR Address Decoding Expansion ROM Address Mapping DecodingMemory 0 Transaction Address Decoding Using the BAR Setup Registers BAR Setup Register ExampleDirect Address Translation Address FormatLookup Table Based Address Translation Direct Offset Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Lookup Table Entry Format Upstream Lookup Table Address TranslationForwarding of 64-Bit Address Memory Transactions Lookup Table Entry FormatI/O Transaction Address Decoding Indirect I/O Transaction GenerationAddress Decoding Configuration Accesses Type 0 Accesses to 21555 Configuration SpaceSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding 21555 Bar Summary Bar SummaryBar Size Address Translation Page PCI Bus Transactions Transactions OverviewPosted Write Transactions Memory Write Transactions Memory Write and Invalidate TransactionsWrite Performance Tuning Options 3 64-bit Extension Posted Write TransactionWrite-Through Delayed Write Transactions Delayed Read Transactions Delayed Write Transaction Target Termination ReturnsTarget Bus Response Initiator Bus Response Delayed Read Transaction Target Termination Returns Nonprefetchable ReadsPrefetchable Read Transactions Using the 64-bit Extension Read Performance Features and Tuning OptionsPrefetchable Reads Prefetching Prefetch BoundariesRead Queue Full Threshold Tuning 64-Bit and 32-Bit Transactions Initiated byTarget Terminations Target Terminations Returned byTransaction Termination Errors on the Target Bus Ordering RulesTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Power Management, Hot-Swap, and Reset Signals Sheet 1Initialization Requirements Reset Behavior Power Management, Hot-Swap, and Reset Signals Sheet 2Spmel SrstinlReset Mechanisms PrstlCentral Function During Reset 21555 InitializationWith SROM, Local, and Host Processors Without Serial PreloadPower Management Support Without Local ProcessorWithout Local Processor and Serial Preload Without Host ProcessorTransitions Between Power Management States Power Management ActionsNext Power State Action 2 PME# SupportPower Management Data Register CompactPCI Hot-Swap FunctionalityOverview of CompactPCI Controller Hardware Interface Insertion and Removal Process Prstl 332 ΩPrimary Lstat K Ω Initialization Requirements W Disconnected W Connected2a INS ENUM# 4b InsertionInitialization Requirements Primary and Secondary PCI Bus Clock Signals Primary and Secondary PCI Bus Clock Signals Sheet 1Signal Name Description ClockingPrimary and Secondary PCI Bus Clock Signals Sheet 2 21555 Secondary Clock OutputsSclk Sclko66 MHz Support Page Interface Signals Parallel ROM InterfaceProm Interface Signals Sheet 1 Signal Type Description NameProm Interface Signals Sheet 2 Prom Read by CSR Access Parallel and Serial ROM Connection21555 WE# OE#Prom Read Timing Prom Write by CSR Access Prom Dword Read Prom Write TimingAccess Time and Strobe Control Read and Write Strobe TimingAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Srom Interface Signals Srom Interface SignalsSerial ROM Interface Sromsrom Preload OperationSrom Configuration Data Preload Format Srom Operation by CSR AccessSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Primary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsSecondary Bus Arbitration Using the Internal Arbiter Primary PCI Bus ArbitrationSecondary PCI Bus Arbitration Secondary Arbiter Example Secondary Bus Arbitration Using an External Arbiter Arbiter Control RegisterBit Name Description Primary and Secondary PCI Bus Interrupt Signals Primary and Secondary PCI Bus Interrupt SignalsInterrupt and Scratchpad Registers Interrupt SupportInterrupt and Scratchpad Registers Doorbell Interrupts Scratchpad RegistersPage Error Handling Error SignalsPrimary PCI Bus Error Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Errors Parity Error Responses Sheet 1Type PER † Action Taken Error Transaction Parity Error Responses Sheet 2 Error TransactionAsserts pperrl Parity Error Responses Sheet 3 Asserts sperrlSystem Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Test Access Port Controller InitializationI2O Support Inbound Message PassingI2O Support Outbound Message Passing 116 117 Page VPD Support Reading VPD InformationWriting VPD Information List of Registers Register SummaryRegister Cross Reference Table Theory of Operation Chapter Register Reference InformationConfiguration Registers Configuration Space Address Register Sheet 1Byte Reset Value Write Read Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Configuration Space Address Register Sheet 5 Register Name Reset Value Write Access Read AccessControl and Status Registers CSR Address Map Sheet 1CSR Address Map Sheet 2 CSR Address Map Sheet 3 Ffff W1TSFfff W1TC CSR Address Map Sheet 4 Address Decoding Primary and Secondary AddressCSR Address Map Sheet 5 Primary CSR and Downstream Memory 0 Bara Sheet 1Primary CSR and Downstream Memory 0 Bara Sheet 2 Secondary CSR Memory BARsa Sheet 1Secondary CSR Memory BARsa Sheet 2 Primary and Secondary CSR I/O BarsaOffsets Primary CSR I/O BAR Secondary CSR I/O BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR OffsetsUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upper 32 Bits Downstream Memory 3 Bar Upstream Memory 2 BarOffsets Downstream I/O or Memory Translated BaseXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Configuration Transaction Generation Registers Upper 32 Bits Downstream Memory 3 Setup RegisterDownstream and Upstream Configuration Address Registers CfgaddrConfiguration Own Bits Register CfgdataConfiguration CSR Sheet 1 Configuration CSR Sheet 2 Downstream I/O Address and Upstream I/O Address RegistersOffset Downstream I/O Address Upstream I/O Address Ioaddr IADownstream I/O Data and Upstream I/O Data Registers O Own Bits RegistersOffsets Downstream I/O Data Upstream I/O Data IodataO CSR Lookup Table Offset RegisterLutoffset Configuration Registers PCI RegistersLookup Table Data Register Upstream Memory 2 Lookup TablePrimary Interface Configuration Space Address Map Secondary Interface Configuration Space Address MapVendor ID Register Device ID RegisterPrimary and Secondary Command Registers Primary and Secondary Command Registers Sheet 1Offsets Primary Command Secondary Command Primary and Secondary Command Registers Sheet 2 Primary and Secondary Status Registers Sheet 1SERR# Offsets Primary Status Secondary StatusPrimary and Secondary Status Registers Sheet 2 Revision ID Rev ID RegisterPrimary and Secondary Class Code Registers Primary and Secondary Cache Line Size RegistersOffsets Primary Class Code Secondary Class Code Offsets Primary Cache Line Size Secondary Cache Line SizeHeader Type Register BiST RegisterOffsets Primary MLT Secondary MLT Subsystem Vendor ID Register Subsystem ID RegisterEnhanced Capabilities Pointer Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Interrupt Pin Registers Primary and Secondary Minimum Grant RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Registers Device-Specific Control and Status Address MapChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Control 1 Register Sheet 3 Chip Status RegisterI20ENA 163 Generic Own Bits Register Rots16.6 I2O Registers I2O Outbound PostList StatusI2O Outbound PostList Interrupt Mask I2O Inbound PostList StatusI2O Inbound PostList Interrupt Mask I2O Inbound QueueI2O Outbound Queue I2OOUT PI2O Inbound FreeList Head Pointer I2O Inbound PostList Tail PointerI2O Outbound FreeList Tail Pointer I2O Outbound PostList Head PointerI2O Inbound PostList Counter I2O Inbound FreeList CounterLdipc W1TLS Ldifc W1TLSI2O Outbound PostList Counter I2O Outbound FreeList CounterLdopc W1TLS Interrupt Registers Chip Status CSRChip Set IRQ Mask Register PMD0 W1TCChip Clear IRQ Mask Register Upstream Page Boundary IRQ 0 RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ 1 Register Upstream Page Boundary IRQ Mask 0 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Clear IRQ and Secondary Clear IRQ Registers Primary Set IRQ and Secondary Set IRQ RegistersPrimary Clear IRQ Secondary Clear IRQ Primary Set IRQPrimary Set IRQ Mask and Secondary Set IRQ Mask Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 1Primary Clear IRQ Mask Secondary Clear IRQ Mask Secondary Set IRQ MaskProm Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 2Primary Expansion ROM BAR Primary Expansion ROM Setup Register Sequence onROM Setup Register ROM Data RegisterRomdata ROM Address Register ROM Control Register Sheet 1Romaddr Mode Setting Configuration Register Sheet 1 Srom RegistersROM Control Register Sheet 2 SrompollMode Setting Configuration Register Sheet 2 Serial Preload Sequence Sheet 1Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Error Registers Arbiter ControlPrimary SERR# Disable Register Secondary SERR# Disable RegisterPower Management ECP ID and Next Pointer Register Init RegistersPM ECP ID Power Management Capabilities Register APSDSI PMEPower Management Control and Status Register Pmcsr Bridge Support ExtensionsPower Management Data Register Reset Control RegisterCompactPCI Hot-Swap Control Register Sheet 1 HS Next PointerJtag Registers CompactPCI Hot-Swap Control Register Sheet 2Jtag Instruction Register Options Sheet 1 Jtag Instruction Register Options Sheet 2 Bypass RegisterBoundary-Scan Register Boundary Scan OrderVPD Registers Vital Product Data VPD ECP ID and Next Pointer RegisterVPD ECP Vital Product Data VPD Address Register VPD Data RegisterPage Acronyms Acronyms Index CSR140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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