Intel 21555 user manual Serial ROM Interface

Page 93

Serial ROM Interface

Prior to a SROM write or write all transaction, the 8-bit write data must be written in the ROM Data CSR.

To initiate the SROM access, the SROM Start bit in the ROM Control CSR is written with a 1 (the PROM Start bit must be written to a 0 with this access). The 21555 then initiates the SROM access. When the SROM access is complete, the 21555 automatically clears the SROM Start bit. When the operation is a read, the data then can be read from the ROM Data register.

The write, write all, erase, and erase all commands may take 10 ms or more to complete, internal to the ROM. A poll of the SROM must be performed to discover whether these operations are complete. For these commands, when the SROM access is initiated, the 21555 also sets the SROM_POLL bit in the Table 112, “ROM Control Register” on page 178. This bit remains asserted after the 21555’s access to the SROM completes. The SROM must be polled by CSR access and return a ready indication to clear the SROM_POLL bit.

The SROM is polled by the 21555 when the SROM Start bit is written with a 1 when the SROM_POLL bit is set. The 21555 asserts sr_cs and drives sr_di (pin pr_ad[1]) low. When the SROM drives sr_do (pin pr_ad[2]) high in response, it has completed the operation internally and the 21555 clears the SROM_POLL bit. The SROM is now ready for another access.

Note: The SROM_POLL bit must be set for the 21555 to poll the SROM, otherwise the 21555 initiates another SROM access if the SROM Start bit is written.

A summary of the actions needed for a SROM read access follows:

1.The initiator writes the byte address and the opcode in the ROM Address CSR.

2.The initiator writes the SROM Start bit to a 1 and the PROM Start bit to a 0 in the ROM Control CSR.

3.When the SROM Start bit in the ROM Control CSR is read as a zero, the initiator may read the 8-bit data from the ROM Data register.

A summary of the actions needed for a write operation follows:

1.The initiator writes the byte address and the opcode in the ROM Address CSR.

2.The initiator writes the 8-bit data in the ROM Data CSR.

3.The initiator writes the SROM Start bit to a 1 and the PROM Start bit to a 0 in the ROM Control CSR in the same CSR access.

4.When the SROM Start bit in the ROM Control CSR is read as a zero, the initiator polls the SROM to test for write completion by writing the SROM Start bit to a 1.

5.When the SROM Start bit in the ROM Control CSR is read as a zero, the SROM_POLL bit indicates the status of the polling operation. When SROM_POLL is read as a one, the SROM should be polled again. When SROM_POLL is read as a 0, the operation is complete.

The erase, erase all, write enable, and write disable all use write protocol. For all of these operations, however, the ROM Data register does not need to be written. In addition, the write enable and write disable operations do not require polling for completion. Figure 19 through Figure 24 show the timing diagrams for SROM read, write, write all, write enable, write disable, erase, erase all, and check status (polling) operations.

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Tables Figures131 148 108 Page Preface Brief description of the contents of this manual followsData Units NumberingTerm Words Bytes Bits Signal Type Abbreviations Signal NomenclatureSignal Description Type STSAccess Type Description Register AbbreviationsRegister Abbreviations Comparing a 21555 to a Transparent PPB IntroductionDram PCI ROM CPUCPU PCI Feature PPB Feature ComparisonData Buffers Architectural OverviewRegisters Control LogicMicroarchitecture Programming Notes Special ApplicationsPrimary Bus VGA Support Secondary Bus VGA SupportTransaction Forwarding ROM AccessPage Signal Descriptions Signal Pin Functional GroupsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Primary PCI Bus Interface Signals Sheet 1Signal Name Type Description Ppar Primary PCI Bus Interface Signals Sheet 2Preql PstoplPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Primary PCI Bus Interface 64-Bit Extension SignalsPack64l Pad6332Ppar64 Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Preq64l Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Sheet 1 Secondary PCI Bus Interface SignalsSpar Secondary PCI Bus Interface Signals Sheet 2Sstopl StrdylSack64l Secondary PCI Bus Interface 64-Bit Extension SignalsSad6332 Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding CSR Address Decoding Expansion ROM Address Mapping DecodingMemory 0 Transaction Address Decoding BAR Setup Register Example Using the BAR Setup RegistersAddress Format Direct Address TranslationDirect Offset Address Translation Lookup Table Based Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Upstream Lookup Table Address Translation Lookup Table Entry FormatLookup Table Entry Format Forwarding of 64-Bit Address Memory TransactionsIndirect I/O Transaction Generation I/O Transaction Address DecodingAddress Decoding Configuration Accesses Type 0 Accesses to 21555 Configuration SpaceSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding 21555 Bar Summary Bar SummaryBar Size Address Translation Page Transactions Overview PCI Bus TransactionsPosted Write Transactions Memory Write and Invalidate Transactions Memory Write Transactions3 64-bit Extension Posted Write Transaction Write Performance Tuning OptionsWrite-Through Delayed Write Transactions Delayed Read Transactions Delayed Write Transaction Target Termination ReturnsTarget Bus Response Initiator Bus Response Nonprefetchable Reads Delayed Read Transaction Target Termination ReturnsPrefetchable Read Transactions Using the 64-bit Extension Read Performance Features and Tuning OptionsPrefetchable Reads Prefetch Boundaries Prefetching64-Bit and 32-Bit Transactions Initiated by Read Queue Full Threshold TuningTarget Terminations Returned by Target TerminationsOrdering Rules Transaction Termination Errors on the Target BusTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Power Management, Hot-Swap, and Reset Signals Sheet 1Initialization Requirements Power Management, Hot-Swap, and Reset Signals Sheet 2 Reset BehaviorSpmel SrstinlPrstl Reset Mechanisms21555 Initialization Central Function During ResetWithout Serial Preload With SROM, Local, and Host ProcessorsWithout Local Processor Power Management SupportWithout Local Processor and Serial Preload Without Host ProcessorPower Management Actions Transitions Between Power Management StatesNext Power State Action 2 PME# SupportPower Management Data Register CompactPCI Hot-Swap FunctionalityOverview of CompactPCI Controller Hardware Interface Insertion and Removal Process Prstl 332 ΩPrimary Lstat K Ω Initialization Requirements W Connected W Disconnected2a INS ENUM# 4b InsertionInitialization Requirements Primary and Secondary PCI Bus Clock Signals Sheet 1 Primary and Secondary PCI Bus Clock SignalsSignal Name Description Clocking21555 Secondary Clock Outputs Primary and Secondary PCI Bus Clock Signals Sheet 2Sclk Sclko66 MHz Support Page Parallel ROM Interface Interface SignalsSignal Type Description Name Prom Interface Signals Sheet 1Prom Interface Signals Sheet 2 Parallel and Serial ROM Connection Prom Read by CSR Access21555 WE# OE#Prom Read Timing Prom Write by CSR Access Prom Write Timing Prom Dword ReadRead and Write Strobe Timing Access Time and Strobe ControlAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Srom Interface Signals Srom Interface SignalsSerial ROM Interface Sromsrom Preload OperationSrom Operation by CSR Access Srom Configuration Data Preload FormatSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Secondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsSecondary Bus Arbitration Using the Internal Arbiter Primary PCI Bus ArbitrationSecondary PCI Bus Arbitration Secondary Arbiter Example Secondary Bus Arbitration Using an External Arbiter Arbiter Control RegisterBit Name Description Primary and Secondary PCI Bus Interrupt Signals Primary and Secondary PCI Bus Interrupt SignalsInterrupt and Scratchpad Registers Interrupt SupportInterrupt and Scratchpad Registers Scratchpad Registers Doorbell InterruptsPage Error Signals Error HandlingPrimary PCI Bus Error Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Errors Parity Error Responses Sheet 1Type PER † Action Taken Error Transaction Parity Error Responses Sheet 2 Error TransactionAsserts pperrl Asserts sperrl Parity Error Responses Sheet 3System Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Initialization Test Access Port ControllerInbound Message Passing I2O SupportI2O Support Outbound Message Passing 116 117 Page Reading VPD Information VPD SupportWriting VPD Information Register Summary List of RegistersRegister Cross Reference Table Theory of Operation Chapter Register Reference InformationConfiguration Space Address Register Sheet 1 Configuration RegistersByte Reset Value Write Read Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Register Name Reset Value Write Access Read Access Configuration Space Address Register Sheet 5Control and Status Registers CSR Address Map Sheet 1CSR Address Map Sheet 2 CSR Address Map Sheet 3 Ffff W1TSFfff W1TC CSR Address Map Sheet 4 Primary and Secondary Address Address DecodingCSR Address Map Sheet 5 Primary CSR and Downstream Memory 0 Bara Sheet 1Secondary CSR Memory BARsa Sheet 1 Primary CSR and Downstream Memory 0 Bara Sheet 2Secondary CSR Memory BARsa Sheet 2 Primary and Secondary CSR I/O BarsaOffsets Primary CSR I/O BAR Secondary CSR I/O BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR OffsetsUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upstream Memory 2 Bar Upper 32 Bits Downstream Memory 3 BarOffsets Downstream I/O or Memory Translated BaseXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Upper 32 Bits Downstream Memory 3 Setup Register Configuration Transaction Generation RegistersCfgaddr Downstream and Upstream Configuration Address RegistersCfgdata Configuration Own Bits RegisterConfiguration CSR Sheet 1 Downstream I/O Address and Upstream I/O Address Registers Configuration CSR Sheet 2Offset Downstream I/O Address Upstream I/O Address Ioaddr IAO Own Bits Registers Downstream I/O Data and Upstream I/O Data RegistersOffsets Downstream I/O Data Upstream I/O Data IodataO CSR Lookup Table Offset RegisterLutoffset PCI Registers Configuration RegistersLookup Table Data Register Upstream Memory 2 Lookup TableSecondary Interface Configuration Space Address Map Primary Interface Configuration Space Address MapVendor ID Register Device ID RegisterPrimary and Secondary Command Registers Primary and Secondary Command Registers Sheet 1Offsets Primary Command Secondary Command Primary and Secondary Status Registers Sheet 1 Primary and Secondary Command Registers Sheet 2SERR# Offsets Primary Status Secondary StatusRevision ID Rev ID Register Primary and Secondary Status Registers Sheet 2Primary and Secondary Cache Line Size Registers Primary and Secondary Class Code RegistersOffsets Primary Class Code Secondary Class Code Offsets Primary Cache Line Size Secondary Cache Line SizeHeader Type Register BiST RegisterOffsets Primary MLT Secondary MLT Subsystem ID Register Subsystem Vendor ID RegisterEnhanced Capabilities Pointer Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Interrupt Pin Registers Primary and Secondary Minimum Grant RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Registers Device-Specific Control and Status Address MapChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Control 1 Register Sheet 3 Chip Status RegisterI20ENA 163 Rots Generic Own Bits RegisterI2O Outbound PostList Status 16.6 I2O RegistersI2O Outbound PostList Interrupt Mask I2O Inbound PostList StatusI2O Inbound Queue I2O Inbound PostList Interrupt MaskI2O Outbound Queue I2OOUT PI2O Inbound PostList Tail Pointer I2O Inbound FreeList Head PointerI2O Outbound FreeList Tail Pointer I2O Outbound PostList Head PointerI2O Inbound FreeList Counter I2O Inbound PostList CounterLdipc W1TLS Ldifc W1TLSI2O Outbound PostList Counter I2O Outbound FreeList CounterLdopc W1TLS Chip Status CSR Interrupt RegistersChip Set IRQ Mask Register PMD0 W1TCChip Clear IRQ Mask Register Upstream Page Boundary IRQ 0 RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ 1 Register Upstream Page Boundary IRQ Mask 0 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Set IRQ and Secondary Set IRQ Registers Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Clear IRQ Secondary Clear IRQ Primary Set IRQScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersPrimary Clear IRQ Mask Secondary Clear IRQ Mask Secondary Set IRQ MaskProm Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 2Primary Expansion ROM BAR Sequence on Primary Expansion ROM Setup RegisterROM Setup Register ROM Data RegisterRomdata ROM Address Register ROM Control Register Sheet 1Romaddr Srom Registers Mode Setting Configuration Register Sheet 1ROM Control Register Sheet 2 SrompollMode Setting Configuration Register Sheet 2 Serial Preload Sequence Sheet 1Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Arbiter Control Error RegistersSecondary SERR# Disable Register Primary SERR# Disable RegisterPower Management ECP ID and Next Pointer Register Init RegistersPM ECP ID APS Power Management Capabilities RegisterDSI PMEPmcsr Bridge Support Extensions Power Management Control and Status RegisterReset Control Register Power Management Data RegisterHS Next Pointer CompactPCI Hot-Swap Control Register Sheet 1Jtag Registers CompactPCI Hot-Swap Control Register Sheet 2Jtag Instruction Register Options Sheet 1 Bypass Register Jtag Instruction Register Options Sheet 2Boundary-Scan Register Boundary Scan OrderVPD Registers Vital Product Data VPD ECP ID and Next Pointer RegisterVPD ECP VPD Data Register Vital Product Data VPD Address RegisterPage Acronyms Acronyms CSR Index140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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