Intel 21555 user manual Prefetching, Prefetch Boundaries

Page 58

PCI Bus Transactions

When using the Quadword boundary, REQ64# asserts every time the transaction is Quadword-aligned (AD[3:0] = x000b). In some cases, the address is only 2 Dwords away from a cache line boundary, or a 4KB boundary. This means that if an ACK64# is not received from the target, another transaction may be necessary to get the high Dword (since FRAME# is only asserted for one cycle, indicating a single data phase).

However, when REQ64# is only asserted when the address is octaword-aligned, instances occur where REQ64# does not assert, but the address is several Dwords from a disconnect or prefetch boundary. For example, when the cache line size is 16 Dwords (32 bytes) but the address is Quadword-aligned on Dword address 2 (xxxx xx08h), there are still 14 Dwords to deliver before the end of a cache line is reached.

Assuming an even distribution of unaligned addresses (which are a minority of all transactions), it is more efficient to optimize for the 64-bit behavior and assert REQ64# on Quadword-aligned accesses, while losing some efficiency on those Quadword-aligned transactions near a boundary where ACK64# is not asserted.

When the bandwidth of the initiator interface is twice that of the target interface, then limited flow-through is allowed. For example, when the initiator is performing a 64-bit transaction, but the corresponding transaction to the target is a 32-bit transaction. In this case, for cache line sizes of 16 and 32 Dwords, flow-through is allowed only when a full cache line is accumulated in the read data buffer for memory read multiple transactions, or when half a cache line is accumulated for memory read line and prefetchable memory read transactions. For cache line sizes of 8 Dwords, flow-through is allowed when 2 Dwords have been accumulated. In limited flow-through only the standard prefetch boundaries described in Prefetching are used, that is, longer bursts are not accommodated. However, limited flow-through minimizes the latency when returning read data with a 2:1 bandwidth mismatch. When the read data queue empties while the 21555 is in limited flow-through mode, the 21555 waits up to seven cycles and then disconnects if read data is still not available.

When the bandwidth of an initiator interface is four times that of the target (e.g., the initiator is performing a 66 MHz, 64-bit operation), and the target is operating at 33 MHz, 32-bit operation, no flow-through is performed. The read operation must complete at the target before read data is returned to the initiator. This is to prevent inserting wait states and possible early disconnects on the initiator bus.

5.4.4.2Prefetching

The 21555 prefetches read data to the aligned address boundaries listed in Table 15.

Table 15. Prefetch Boundaries

Read Command

Non-prefetchable

Prefetchable

In Flow-Through Mode

Range

Range

 

 

 

 

 

 

 

 

 

Page boundary for transactions in Upstream

Memory Read

1 Dword

1 cache line

Memory 2 range

4KB boundary

 

 

 

 

 

 

Initiator deasserts FRAME#

 

 

 

 

 

 

 

Page boundary for transactions in Upstream

Memory Read Line

1 cache line

1 cache line

Memory 2 range

4 KB boundary

 

 

 

 

 

 

Initiator deasserts FRAME#

 

 

 

 

 

 

 

Page boundary for transactions in Upstream

Memory Read

2 cache lines

2 cache lines

Memory 2 range

 

Multiple

4 KB boundary

 

 

 

 

 

Initiator deasserts FRAME#

 

 

 

 

The cache line size corresponding to the initiator bus is used for determining prefetch boundaries.

58

21555 Non-Transparent PCI-to-PCI Bridge User Manual

Page 57 Page 59
Image 58
Page 57 Page 59
Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Figures Tables131 148 108 Page Brief description of the contents of this manual follows PrefaceNumbering Data UnitsTerm Words Bytes Bits Signal Description Type Signal NomenclatureSignal Type Abbreviations STSRegister Abbreviations Access Type DescriptionRegister Abbreviations Introduction Comparing a 21555 to a Transparent PPBCPU Dram PCI ROMCPU PCI PPB Feature Comparison FeatureRegisters Architectural OverviewData Buffers Control LogicMicroarchitecture Primary Bus VGA Support Special ApplicationsProgramming Notes Secondary Bus VGA SupportROM Access Transaction ForwardingPage Signal Pin Functional Groups Signal DescriptionsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Sheet 1 Primary PCI Bus Interface SignalsSignal Name Type Description Preql Primary PCI Bus Interface Signals Sheet 2Ppar PstoplPack64l Primary PCI Bus Interface 64-Bit Extension SignalsPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Pad6332Preq64l Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Ppar64 Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Secondary PCI Bus Interface Signals Sheet 1Sstopl Secondary PCI Bus Interface Signals Sheet 2Spar StrdylSad6332 Secondary PCI Bus Interface 64-Bit Extension SignalsSack64l Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Expansion ROM Address Mapping Decoding CSR Address DecodingMemory 0 Transaction Address Decoding Using the BAR Setup Registers BAR Setup Register ExampleDirect Address Translation Address FormatLookup Table Based Address Translation Direct Offset Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Lookup Table Entry Format Upstream Lookup Table Address TranslationForwarding of 64-Bit Address Memory Transactions Lookup Table Entry FormatI/O Transaction Address Decoding Indirect I/O Transaction GenerationAddress Decoding Type 0 Accesses to 21555 Configuration Space Configuration AccessesSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding Bar Summary 21555 Bar SummaryBar Size Address Translation Page PCI Bus Transactions Transactions OverviewPosted Write Transactions Memory Write Transactions Memory Write and Invalidate TransactionsWrite Performance Tuning Options 3 64-bit Extension Posted Write TransactionWrite-Through Delayed Write Transactions Delayed Write Transaction Target Termination Returns Delayed Read TransactionsTarget Bus Response Initiator Bus Response Delayed Read Transaction Target Termination Returns Nonprefetchable ReadsRead Performance Features and Tuning Options Prefetchable Read Transactions Using the 64-bit ExtensionPrefetchable Reads Prefetching Prefetch BoundariesRead Queue Full Threshold Tuning 64-Bit and 32-Bit Transactions Initiated byTarget Terminations Target Terminations Returned byTransaction Termination Errors on the Target Bus Ordering RulesTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Sheet 1 Power Management, Hot-Swap, and Reset SignalsInitialization Requirements Spmel Reset BehaviorPower Management, Hot-Swap, and Reset Signals Sheet 2 SrstinlReset Mechanisms PrstlCentral Function During Reset 21555 InitializationWith SROM, Local, and Host Processors Without Serial PreloadWithout Local Processor and Serial Preload Power Management SupportWithout Local Processor Without Host ProcessorNext Power State Action Transitions Between Power Management StatesPower Management Actions 2 PME# SupportCompactPCI Hot-Swap Functionality Power Management Data RegisterOverview of CompactPCI Controller Hardware Interface Prstl 332 Ω Insertion and Removal ProcessPrimary Lstat K Ω Initialization Requirements 2a INS ENUM# W DisconnectedW Connected 4b InsertionInitialization Requirements Signal Name Description Primary and Secondary PCI Bus Clock SignalsPrimary and Secondary PCI Bus Clock Signals Sheet 1 ClockingSclk Primary and Secondary PCI Bus Clock Signals Sheet 221555 Secondary Clock Outputs Sclko66 MHz Support Page Interface Signals Parallel ROM InterfaceProm Interface Signals Sheet 1 Signal Type Description NameProm Interface Signals Sheet 2 21555 Prom Read by CSR AccessParallel and Serial ROM Connection WE# OE#Prom Read Timing Prom Write by CSR Access Prom Dword Read Prom Write TimingAccess Time and Strobe Control Read and Write Strobe TimingAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Serial ROM Interface Srom Interface SignalsSrom Interface Signals Sromsrom Preload OperationSrom Configuration Data Preload Format Srom Operation by CSR AccessSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Primary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterSecondary PCI Bus Arbitration Secondary Arbiter Example Arbiter Control Register Secondary Bus Arbitration Using an External ArbiterBit Name Description Interrupt and Scratchpad Registers Primary and Secondary PCI Bus Interrupt SignalsPrimary and Secondary PCI Bus Interrupt Signals Interrupt SupportInterrupt and Scratchpad Registers Doorbell Interrupts Scratchpad RegistersPage Primary PCI Bus Error Signals Error HandlingError Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Error Responses Sheet 1 Parity ErrorsType PER † Action Taken Error Transaction Error Transaction Parity Error Responses Sheet 2Asserts pperrl Parity Error Responses Sheet 3 Asserts sperrlSystem Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Test Access Port Controller InitializationI2O Support Inbound Message PassingI2O Support Outbound Message Passing 116 117 Page VPD Support Reading VPD InformationWriting VPD Information Register Cross Reference Table List of RegistersRegister Summary Theory of Operation Chapter Register Reference InformationByte Reset Value Write Read Configuration RegistersConfiguration Space Address Register Sheet 1 Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Control and Status Registers Configuration Space Address Register Sheet 5Register Name Reset Value Write Access Read Access CSR Address Map Sheet 1CSR Address Map Sheet 2 Ffff W1TS CSR Address Map Sheet 3Ffff W1TC CSR Address Map Sheet 4 CSR Address Map Sheet 5 Address DecodingPrimary and Secondary Address Primary CSR and Downstream Memory 0 Bara Sheet 1Primary CSR and Downstream Memory 0 Bara Sheet 2 Secondary CSR Memory BARsa Sheet 1Primary and Secondary CSR I/O Barsa Secondary CSR Memory BARsa Sheet 2Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Offsets Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BARUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upper 32 Bits Downstream Memory 3 Bar Upstream Memory 2 BarTranslated Base Offsets Downstream I/O or MemoryXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Configuration Transaction Generation Registers Upper 32 Bits Downstream Memory 3 Setup RegisterDownstream and Upstream Configuration Address Registers CfgaddrConfiguration Own Bits Register CfgdataConfiguration CSR Sheet 1 Offset Downstream I/O Address Upstream I/O Address Configuration CSR Sheet 2Downstream I/O Address and Upstream I/O Address Registers Ioaddr IAOffsets Downstream I/O Data Upstream I/O Data Downstream I/O Data and Upstream I/O Data RegistersO Own Bits Registers IodataLookup Table Offset Register O CSRLutoffset Lookup Table Data Register Configuration RegistersPCI Registers Upstream Memory 2 Lookup TableVendor ID Register Primary Interface Configuration Space Address MapSecondary Interface Configuration Space Address Map Device ID RegisterPrimary and Secondary Command Registers Sheet 1 Primary and Secondary Command RegistersOffsets Primary Command Secondary Command SERR# Primary and Secondary Command Registers Sheet 2Primary and Secondary Status Registers Sheet 1 Offsets Primary Status Secondary StatusPrimary and Secondary Status Registers Sheet 2 Revision ID Rev ID RegisterOffsets Primary Class Code Secondary Class Code Primary and Secondary Class Code RegistersPrimary and Secondary Cache Line Size Registers Offsets Primary Cache Line Size Secondary Cache Line SizeBiST Register Header Type RegisterOffsets Primary MLT Secondary MLT Enhanced Capabilities Pointer Register Subsystem Vendor ID RegisterSubsystem ID Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Minimum Grant Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Address Map Device-Specific Control and Status RegistersChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Status Register Chip Control 1 Register Sheet 3I20ENA 163 Generic Own Bits Register RotsI2O Outbound PostList Interrupt Mask 16.6 I2O RegistersI2O Outbound PostList Status I2O Inbound PostList StatusI2O Outbound Queue I2O Inbound PostList Interrupt MaskI2O Inbound Queue I2OOUT PI2O Outbound FreeList Tail Pointer I2O Inbound FreeList Head PointerI2O Inbound PostList Tail Pointer I2O Outbound PostList Head PointerLdipc W1TLS I2O Inbound PostList CounterI2O Inbound FreeList Counter Ldifc W1TLSI2O Outbound FreeList Counter I2O Outbound PostList CounterLdopc W1TLS Chip Set IRQ Mask Register Interrupt RegistersChip Status CSR PMD0 W1TCUpstream Page Boundary IRQ 0 Register Chip Clear IRQ Mask RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ Mask 0 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Clear IRQ Secondary Clear IRQ Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Set IRQ and Secondary Set IRQ Registers Primary Set IRQPrimary Clear IRQ Mask Secondary Clear IRQ Mask Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Secondary Set IRQ MaskScratchpad 0 Through Scratchpad 7 Registers Sheet 2 Prom RegistersPrimary Expansion ROM BAR Primary Expansion ROM Setup Register Sequence onROM Data Register ROM Setup RegisterRomdata ROM Control Register Sheet 1 ROM Address RegisterRomaddr ROM Control Register Sheet 2 Mode Setting Configuration Register Sheet 1Srom Registers SrompollSerial Preload Sequence Sheet 1 Mode Setting Configuration Register Sheet 2Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Error Registers Arbiter ControlPrimary SERR# Disable Register Secondary SERR# Disable RegisterInit Registers Power Management ECP ID and Next Pointer RegisterPM ECP ID DSI Power Management Capabilities RegisterAPS PMEPower Management Control and Status Register Pmcsr Bridge Support ExtensionsPower Management Data Register Reset Control RegisterCompactPCI Hot-Swap Control Register Sheet 1 HS Next PointerCompactPCI Hot-Swap Control Register Sheet 2 Jtag RegistersJtag Instruction Register Options Sheet 1 Boundary-Scan Register Jtag Instruction Register Options Sheet 2Bypass Register Boundary Scan OrderVital Product Data VPD ECP ID and Next Pointer Register VPD RegistersVPD ECP Vital Product Data VPD Address Register VPD Data RegisterPage Acronyms Acronyms Index CSR140
Related manuals
Manual 26 pages 60.05 Kb

21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
Top Page Image Contents