Intel 21555 Interrupt and Scratchpad Registers, Primary and Secondary PCI Bus Interrupt Signals

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Interrupt and Scratchpad Registers 11

This chapter presents the theory of operation information about the 21555 interrupt handling and about the 32-bit scratchpad registers. See Chapter 16 for specific information about these registers.

11.1Primary and Secondary PCI Bus Interrupt Signals

Table 26 describes the primary and secondary PCI bus interrupt signals.

Table 26. Primary and Secondary PCI Bus Interrupt Signals

Signal Name

Type

Description

 

 

 

 

 

Primary PCI bus interrupt. Signal p_inta_l is asserted by the 21555 when:

 

 

A primary doorbell register bit is set.

p_inta_l

 

The I20 outbound queue is not empty.

OD

The subsystem event bit is set.

 

 

 

 

All of these conditions are individually maskable. When the corresponding event bit is

 

 

cleared or the I20 outbound queue is emptied, p_inta_l is deasserted. Signal p_inta_l

 

 

is pulled up through an external resistor.

 

 

 

 

 

Secondary PCI bus interrupt. Signal s_inta_l is asserted by the 21555 when:

 

 

A secondary doorbell register bit is set.

 

 

The I20 inbound queue is not empty.

s_inta_l

OD

A page boundary is reached when performing lookup table address translation.

The 21555 transitions from a D1 or D2 power state to a D0 power state.

 

 

 

 

All of these conditions are individually maskable. Signal s_inta_l is deasserted when

 

 

the corresponding event bit is cleared, or when the I20 inbound queue is empty.

 

 

Signal s_inta_l is pulled up through an external resistor.

 

 

 

11.2Interrupt Support

The 21555 supports hardware to facilitate software-generated interrupts, as well as interrupts initiated by the 21555 activity. The 21555 has interrupt request status and interrupt mask bits for the following conditions:

•I20 Inbound Post_List FIFO not empty.

—Cleared automatically when FIFO is empty.

—Asserts s_inta_l when the corresponding mask bit is zero.

•I20 Outbound Post_List FIFO not empty.

—Cleared automatically when FIFO is empty.

—Asserts p_inta_l when the corresponding mask bit is zero.

•Upstream memory read or write Dword transfer in Upstream Memory Range 2 addresses the last Dword in a page.

—One event and enable bit for each of the 64 pages in Upstream Memory Range 2.

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Tables Figures131 148 108 Page Preface Brief description of the contents of this manual followsTerm Words Bytes Bits Data UnitsNumbering Signal Type Abbreviations Signal NomenclatureSignal Description Type STSRegister Abbreviations Access Type DescriptionRegister Abbreviations Comparing a 21555 to a Transparent PPB IntroductionCPU PCI Dram PCI ROMCPU Feature PPB Feature ComparisonData Buffers Architectural OverviewRegisters Control LogicMicroarchitecture Programming Notes Special ApplicationsPrimary Bus VGA Support Secondary Bus VGA SupportTransaction Forwarding ROM AccessPage Group by Signal Pin Description See Signal DescriptionsSignal Pin Functional Groups Signal Name Type Description Primary PCI Bus Interface SignalsPrimary PCI Bus Interface Signals Sheet 1 Ppar Primary PCI Bus Interface Signals Sheet 2Preql PstoplPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Primary PCI Bus Interface 64-Bit Extension SignalsPack64l Pad6332Ppar64 Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Preq64l Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Sheet 1 Secondary PCI Bus Interface SignalsSpar Secondary PCI Bus Interface Signals Sheet 2Sstopl StrdylSack64l Secondary PCI Bus Interface 64-Bit Extension SignalsSad6332 Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Memory 0 Transaction Address Decoding CSR Address DecodingExpansion ROM Address Mapping Decoding BAR Setup Register Example Using the BAR Setup RegistersAddress Format Direct Address TranslationDirect Offset Address Translation Lookup Table Based Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Upstream Lookup Table Address Translation Lookup Table Entry FormatLookup Table Entry Format Forwarding of 64-Bit Address Memory TransactionsIndirect I/O Transaction Generation I/O Transaction Address DecodingAddress Decoding Subtractive Decoding of I/O Transactions Configuration AccessesType 0 Accesses to 21555 Configuration Space Initiation of Configuration Transactions by Address Decoding Bar Size Address Translation 21555 Bar SummaryBar Summary Page Transactions Overview PCI Bus TransactionsPosted Write Transactions Memory Write and Invalidate Transactions Memory Write Transactions3 64-bit Extension Posted Write Transaction Write Performance Tuning OptionsWrite-Through Delayed Write Transactions Target Bus Response Initiator Bus Response Delayed Read TransactionsDelayed Write Transaction Target Termination Returns Nonprefetchable Reads Delayed Read Transaction Target Termination ReturnsPrefetchable Reads Prefetchable Read Transactions Using the 64-bit ExtensionRead Performance Features and Tuning Options Prefetch Boundaries Prefetching64-Bit and 32-Bit Transactions Initiated by Read Queue Full Threshold TuningTarget Terminations Returned by Target TerminationsOrdering Rules Transaction Termination Errors on the Target BusTransaction Ordering Rules PCI Bus Transactions Page Initialization Requirements Power Management, Hot-Swap, and Reset SignalsPower Management, Hot-Swap, and Reset Signals Sheet 1 Power Management, Hot-Swap, and Reset Signals Sheet 2 Reset BehaviorSpmel SrstinlPrstl Reset Mechanisms21555 Initialization Central Function During ResetWithout Serial Preload With SROM, Local, and Host ProcessorsWithout Local Processor Power Management SupportWithout Local Processor and Serial Preload Without Host ProcessorPower Management Actions Transitions Between Power Management StatesNext Power State Action 2 PME# SupportOverview of CompactPCI Controller Hardware Interface Power Management Data RegisterCompactPCI Hot-Swap Functionality Primary Lstat K Ω Insertion and Removal ProcessPrstl 332 Ω Initialization Requirements W Connected W Disconnected2a INS ENUM# 4b InsertionInitialization Requirements Primary and Secondary PCI Bus Clock Signals Sheet 1 Primary and Secondary PCI Bus Clock SignalsSignal Name Description Clocking21555 Secondary Clock Outputs Primary and Secondary PCI Bus Clock Signals Sheet 2Sclk Sclko66 MHz Support Page Parallel ROM Interface Interface SignalsSignal Type Description Name Prom Interface Signals Sheet 1Prom Interface Signals Sheet 2 Parallel and Serial ROM Connection Prom Read by CSR Access21555 WE# OE#Prom Read Timing Prom Write by CSR Access Prom Write Timing Prom Dword ReadRead and Write Strobe Timing Access Time and Strobe ControlAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Srom Interface Signals Srom Interface SignalsSerial ROM Interface Sromsrom Preload OperationSrom Operation by CSR Access Srom Configuration Data Preload FormatSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Secondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterPrimary PCI Bus Arbitration Secondary Arbiter Example Bit Name Description Secondary Bus Arbitration Using an External ArbiterArbiter Control Register Primary and Secondary PCI Bus Interrupt Signals Primary and Secondary PCI Bus Interrupt SignalsInterrupt and Scratchpad Registers Interrupt SupportInterrupt and Scratchpad Registers Scratchpad Registers Doorbell InterruptsPage Error Signals Error HandlingPrimary PCI Bus Error Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Type PER † Action Taken Error Transaction Parity ErrorsParity Error Responses Sheet 1 Asserts pperrl Parity Error Responses Sheet 2Error Transaction Asserts sperrl Parity Error Responses Sheet 3System Error SERR# Reporting Jtag Test Port Jtag SignalsJtag Signals Initialization Test Access Port ControllerInbound Message Passing I2O SupportI2O Support Outbound Message Passing 116 117 Page Reading VPD Information VPD SupportWriting VPD Information Register Summary List of RegistersRegister Cross Reference Table Theory of Operation Chapter Register Reference InformationConfiguration Space Address Register Sheet 1 Configuration RegistersByte Reset Value Write Read Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Register Name Reset Value Write Access Read Access Configuration Space Address Register Sheet 5Control and Status Registers CSR Address Map Sheet 1CSR Address Map Sheet 2 Ffff W1TC CSR Address Map Sheet 3Ffff W1TS CSR Address Map Sheet 4 Primary and Secondary Address Address DecodingCSR Address Map Sheet 5 Primary CSR and Downstream Memory 0 Bara Sheet 1Secondary CSR Memory BARsa Sheet 1 Primary CSR and Downstream Memory 0 Bara Sheet 2Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Secondary CSR Memory BARsa Sheet 2Primary and Secondary CSR I/O Barsa Upstream I/O or Memory 0 BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAROffsets Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upstream Memory 2 Bar Upper 32 Bits Downstream Memory 3 BarXlatbase Offsets Downstream I/O or MemoryTranslated Base Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Upper 32 Bits Downstream Memory 3 Setup Register Configuration Transaction Generation RegistersCfgaddr Downstream and Upstream Configuration Address RegistersCfgdata Configuration Own Bits RegisterConfiguration CSR Sheet 1 Downstream I/O Address and Upstream I/O Address Registers Configuration CSR Sheet 2Offset Downstream I/O Address Upstream I/O Address Ioaddr IAO Own Bits Registers Downstream I/O Data and Upstream I/O Data RegistersOffsets Downstream I/O Data Upstream I/O Data IodataLutoffset O CSRLookup Table Offset Register PCI Registers Configuration RegistersLookup Table Data Register Upstream Memory 2 Lookup TableSecondary Interface Configuration Space Address Map Primary Interface Configuration Space Address MapVendor ID Register Device ID RegisterOffsets Primary Command Secondary Command Primary and Secondary Command RegistersPrimary and Secondary Command Registers Sheet 1 Primary and Secondary Status Registers Sheet 1 Primary and Secondary Command Registers Sheet 2SERR# Offsets Primary Status Secondary StatusRevision ID Rev ID Register Primary and Secondary Status Registers Sheet 2Primary and Secondary Cache Line Size Registers Primary and Secondary Class Code RegistersOffsets Primary Class Code Secondary Class Code Offsets Primary Cache Line Size Secondary Cache Line SizeOffsets Primary MLT Secondary MLT Header Type RegisterBiST Register Subsystem ID Register Subsystem Vendor ID RegisterEnhanced Capabilities Pointer Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Maximum Latency Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Minimum Grant Registers Chip Control 0 Register Sheet 1 Device-Specific Control and Status RegistersDevice-Specific Control and Status Address Map Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 I20ENA Chip Control 1 Register Sheet 3Chip Status Register 163 Rots Generic Own Bits RegisterI2O Outbound PostList Status 16.6 I2O RegistersI2O Outbound PostList Interrupt Mask I2O Inbound PostList StatusI2O Inbound Queue I2O Inbound PostList Interrupt MaskI2O Outbound Queue I2OOUT PI2O Inbound PostList Tail Pointer I2O Inbound FreeList Head PointerI2O Outbound FreeList Tail Pointer I2O Outbound PostList Head PointerI2O Inbound FreeList Counter I2O Inbound PostList CounterLdipc W1TLS Ldifc W1TLSLdopc W1TLS I2O Outbound PostList CounterI2O Outbound FreeList Counter Chip Status CSR Interrupt RegistersChip Set IRQ Mask Register PMD0 W1TCPAGE0IRQ W1TC Chip Clear IRQ Mask RegisterUpstream Page Boundary IRQ 0 Register Upstream Page Boundary IRQ Mask 1 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 0 Register Primary Set IRQ and Secondary Set IRQ Registers Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Clear IRQ Secondary Clear IRQ Primary Set IRQScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersPrimary Clear IRQ Mask Secondary Clear IRQ Mask Secondary Set IRQ MaskPrimary Expansion ROM BAR Prom RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 2 Sequence on Primary Expansion ROM Setup RegisterRomdata ROM Setup RegisterROM Data Register Romaddr ROM Address RegisterROM Control Register Sheet 1 Srom Registers Mode Setting Configuration Register Sheet 1ROM Control Register Sheet 2 SrompollByte Description Offset Mode Setting Configuration Register Sheet 2Serial Preload Sequence Sheet 1 Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Arbiter Control Error RegistersSecondary SERR# Disable Register Primary SERR# Disable RegisterPM ECP ID Power Management ECP ID and Next Pointer RegisterInit Registers APS Power Management Capabilities RegisterDSI PMEPmcsr Bridge Support Extensions Power Management Control and Status RegisterReset Control Register Power Management Data RegisterHS Next Pointer CompactPCI Hot-Swap Control Register Sheet 1Jtag Instruction Register Options Sheet 1 Jtag RegistersCompactPCI Hot-Swap Control Register Sheet 2 Bypass Register Jtag Instruction Register Options Sheet 2Boundary-Scan Register Boundary Scan OrderVPD ECP VPD RegistersVital Product Data VPD ECP ID and Next Pointer Register VPD Data Register Vital Product Data VPD Address RegisterPage Acronyms Acronyms CSR Index140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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