Intel 21555 user manual Ordering Rules, Transaction Termination Errors on the Target Bus

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PCI Bus Transactions

5.6.2Transaction Termination Errors on the Target Bus

When the 21555 detects a target abort on the target bus, the 21555 sets the Received Target Abort in the Primary and Secondary Status register. See Table 62, “Primary and Secondary Status Registers” on page 150. In addition, the 21555:

•For delayed transactions, returns a target abort to the initiator and sets the Signaled Target Abort bit in the Primary and Secondary Status register.

•For posted write transactions, asserts SERR# on the initiator bus if the SERR# Enable for that interface is set, and sets the Signaled System Error bit in the Primary and Secondary Status register.

When the 21555 detects a master abort on the target bus, the 21555 always sets Received Master Abort bit in Primary and Secondary Status register. In addition, the 21555:

•For delayed transactions when the Master Abort Mode bit is 0, returns TRDY# and, for reads, FFFFFFFFh to the initiator. See Table 77, “Chip Control 0 Register” on page 156.

•For delayed transactions when the Master Abort Mode bit is 1, returns a target abort and sets the Signaled Target Abort bit in the Primary and Secondary Status register.

•For posted write transactions, assert SERR# and set the Signaled System Error bit on the initiator bus if the SERR# Enable for that interface is set and the SERR# Disable for Master Abort during Posted Write is clear.

5.7Ordering Rules

The 21555 can queue and forward multiple transactions at once. Therefore, at any one time the 21555 has multiple posted write and multiple delayed transaction requests and completions queued and traveling in the same and opposite directions. The 21555 uses a set of ordering rules to dictate the order in which it initiates posted writes, initiates delayed transaction requests, and returns delayed transaction completion status. These rules reflect both the ordering constraints outlined in the PCI Local Bus Specification, Revision 2.2 as well as implementation choices specific to the 21555.

Independent transactions on the primary and secondary buses only have a relationship when those transactions cross the 21555. General ordering guidelines for transactions crossing the 21555 are:

•The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes; that is, when a transaction ends with a termination other than target retry.

•Requests terminated with target retry may be accepted and completed in any order with respect to other transactions that have been terminated with target retry. When the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. When more than one delayed transaction is initiated, the initiator should repeat all the delayed transaction requests using some fairness algorithm; that is, reattempting a delayed transaction cannot be contingent on completion of another delayed transaction, otherwise a deadlock can occur. This deadlock is avoided with an out-of-order delivery and completion.

•Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. The 21555 can accept posted writes on both interfaces at the same time, as well as initiate posted writes on both interfaces at the same time.

•The acceptance of a posted memory write as a target can never be contingent on the completion of a non-posted transaction as a master. This is true of the 21555 and must also be true of other bus agents; otherwise, a deadlock can occur.

•The 21555 accepts posted writes regardless of the state of completion of any delayed transactions being forwarded across the bridge.

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Tables Figures131 148 108 Page Preface Brief description of the contents of this manual followsNumbering Data UnitsTerm Words Bytes Bits Signal Type Abbreviations Signal NomenclatureSignal Description Type STSRegister Abbreviations Access Type DescriptionRegister Abbreviations Comparing a 21555 to a Transparent PPB IntroductionCPU Dram PCI ROMCPU PCI Feature PPB Feature ComparisonData Buffers Architectural OverviewRegisters Control LogicMicroarchitecture Programming Notes Special ApplicationsPrimary Bus VGA Support Secondary Bus VGA SupportTransaction Forwarding ROM AccessPage Signal Pin Functional Groups Signal DescriptionsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Sheet 1 Primary PCI Bus Interface SignalsSignal Name Type Description Ppar Primary PCI Bus Interface Signals Sheet 2Preql PstoplPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Primary PCI Bus Interface 64-Bit Extension SignalsPack64l Pad6332Ppar64 Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Preq64l Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Sheet 1 Secondary PCI Bus Interface SignalsSpar Secondary PCI Bus Interface Signals Sheet 2Sstopl StrdylSack64l Secondary PCI Bus Interface 64-Bit Extension SignalsSad6332 Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Expansion ROM Address Mapping Decoding CSR Address DecodingMemory 0 Transaction Address Decoding BAR Setup Register Example Using the BAR Setup RegistersAddress Format Direct Address TranslationDirect Offset Address Translation Lookup Table Based Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Upstream Lookup Table Address Translation Lookup Table Entry FormatLookup Table Entry Format Forwarding of 64-Bit Address Memory TransactionsIndirect I/O Transaction Generation I/O Transaction Address DecodingAddress Decoding Type 0 Accesses to 21555 Configuration Space Configuration AccessesSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding Bar Summary 21555 Bar SummaryBar Size Address Translation Page Transactions Overview PCI Bus TransactionsPosted Write Transactions Memory Write and Invalidate Transactions Memory Write Transactions3 64-bit Extension Posted Write Transaction Write Performance Tuning OptionsWrite-Through Delayed Write Transactions Delayed Write Transaction Target Termination Returns Delayed Read TransactionsTarget Bus Response Initiator Bus Response Nonprefetchable Reads Delayed Read Transaction Target Termination ReturnsRead Performance Features and Tuning Options Prefetchable Read Transactions Using the 64-bit ExtensionPrefetchable Reads Prefetch Boundaries Prefetching64-Bit and 32-Bit Transactions Initiated by Read Queue Full Threshold TuningTarget Terminations Returned by Target TerminationsOrdering Rules Transaction Termination Errors on the Target BusTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Sheet 1 Power Management, Hot-Swap, and Reset SignalsInitialization Requirements Power Management, Hot-Swap, and Reset Signals Sheet 2 Reset BehaviorSpmel SrstinlPrstl Reset Mechanisms21555 Initialization Central Function During ResetWithout Serial Preload With SROM, Local, and Host ProcessorsWithout Local Processor Power Management SupportWithout Local Processor and Serial Preload Without Host ProcessorPower Management Actions Transitions Between Power Management StatesNext Power State Action 2 PME# SupportCompactPCI Hot-Swap Functionality Power Management Data RegisterOverview of CompactPCI Controller Hardware Interface Prstl 332 Ω Insertion and Removal ProcessPrimary Lstat K Ω Initialization Requirements W Connected W Disconnected2a INS ENUM# 4b InsertionInitialization Requirements Primary and Secondary PCI Bus Clock Signals Sheet 1 Primary and Secondary PCI Bus Clock SignalsSignal Name Description Clocking21555 Secondary Clock Outputs Primary and Secondary PCI Bus Clock Signals Sheet 2Sclk Sclko66 MHz Support Page Parallel ROM Interface Interface SignalsSignal Type Description Name Prom Interface Signals Sheet 1Prom Interface Signals Sheet 2 Parallel and Serial ROM Connection Prom Read by CSR Access21555 WE# OE#Prom Read Timing Prom Write by CSR Access Prom Write Timing Prom Dword ReadRead and Write Strobe Timing Access Time and Strobe ControlAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Srom Interface Signals Srom Interface SignalsSerial ROM Interface Sromsrom Preload OperationSrom Operation by CSR Access Srom Configuration Data Preload FormatSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Secondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterSecondary PCI Bus Arbitration Secondary Arbiter Example Arbiter Control Register Secondary Bus Arbitration Using an External ArbiterBit Name Description Primary and Secondary PCI Bus Interrupt Signals Primary and Secondary PCI Bus Interrupt SignalsInterrupt and Scratchpad Registers Interrupt SupportInterrupt and Scratchpad Registers Scratchpad Registers Doorbell InterruptsPage Error Signals Error HandlingPrimary PCI Bus Error Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Error Responses Sheet 1 Parity ErrorsType PER † Action Taken Error Transaction Error Transaction Parity Error Responses Sheet 2Asserts pperrl Asserts sperrl Parity Error Responses Sheet 3System Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Initialization Test Access Port ControllerInbound Message Passing I2O SupportI2O Support Outbound Message Passing 116 117 Page Reading VPD Information VPD SupportWriting VPD Information Register Summary List of RegistersRegister Cross Reference Table Theory of Operation Chapter Register Reference InformationConfiguration Space Address Register Sheet 1 Configuration RegistersByte Reset Value Write Read Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Register Name Reset Value Write Access Read Access Configuration Space Address Register Sheet 5Control and Status Registers CSR Address Map Sheet 1CSR Address Map Sheet 2 Ffff W1TS CSR Address Map Sheet 3Ffff W1TC CSR Address Map Sheet 4 Primary and Secondary Address Address DecodingCSR Address Map Sheet 5 Primary CSR and Downstream Memory 0 Bara Sheet 1Secondary CSR Memory BARsa Sheet 1 Primary CSR and Downstream Memory 0 Bara Sheet 2Primary and Secondary CSR I/O Barsa Secondary CSR Memory BARsa Sheet 2Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Offsets Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BARUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upstream Memory 2 Bar Upper 32 Bits Downstream Memory 3 BarTranslated Base Offsets Downstream I/O or MemoryXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Upper 32 Bits Downstream Memory 3 Setup Register Configuration Transaction Generation RegistersCfgaddr Downstream and Upstream Configuration Address RegistersCfgdata Configuration Own Bits RegisterConfiguration CSR Sheet 1 Downstream I/O Address and Upstream I/O Address Registers Configuration CSR Sheet 2Offset Downstream I/O Address Upstream I/O Address Ioaddr IAO Own Bits Registers Downstream I/O Data and Upstream I/O Data RegistersOffsets Downstream I/O Data Upstream I/O Data IodataLookup Table Offset Register O CSRLutoffset PCI Registers Configuration RegistersLookup Table Data Register Upstream Memory 2 Lookup TableSecondary Interface Configuration Space Address Map Primary Interface Configuration Space Address MapVendor ID Register Device ID RegisterPrimary and Secondary Command Registers Sheet 1 Primary and Secondary Command RegistersOffsets Primary Command Secondary Command Primary and Secondary Status Registers Sheet 1 Primary and Secondary Command Registers Sheet 2SERR# Offsets Primary Status Secondary StatusRevision ID Rev ID Register Primary and Secondary Status Registers Sheet 2Primary and Secondary Cache Line Size Registers Primary and Secondary Class Code RegistersOffsets Primary Class Code Secondary Class Code Offsets Primary Cache Line Size Secondary Cache Line SizeBiST Register Header Type RegisterOffsets Primary MLT Secondary MLT Subsystem ID Register Subsystem Vendor ID RegisterEnhanced Capabilities Pointer Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Minimum Grant Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Address Map Device-Specific Control and Status RegistersChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Status Register Chip Control 1 Register Sheet 3I20ENA 163 Rots Generic Own Bits RegisterI2O Outbound PostList Status 16.6 I2O RegistersI2O Outbound PostList Interrupt Mask I2O Inbound PostList StatusI2O Inbound Queue I2O Inbound PostList Interrupt MaskI2O Outbound Queue I2OOUT PI2O Inbound PostList Tail Pointer I2O Inbound FreeList Head PointerI2O Outbound FreeList Tail Pointer I2O Outbound PostList Head PointerI2O Inbound FreeList Counter I2O Inbound PostList CounterLdipc W1TLS Ldifc W1TLSI2O Outbound FreeList Counter I2O Outbound PostList CounterLdopc W1TLS Chip Status CSR Interrupt RegistersChip Set IRQ Mask Register PMD0 W1TCUpstream Page Boundary IRQ 0 Register Chip Clear IRQ Mask RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ Mask 0 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Set IRQ and Secondary Set IRQ Registers Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Clear IRQ Secondary Clear IRQ Primary Set IRQScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersPrimary Clear IRQ Mask Secondary Clear IRQ Mask Secondary Set IRQ MaskScratchpad 0 Through Scratchpad 7 Registers Sheet 2 Prom RegistersPrimary Expansion ROM BAR Sequence on Primary Expansion ROM Setup RegisterROM Data Register ROM Setup RegisterRomdata ROM Control Register Sheet 1 ROM Address RegisterRomaddr Srom Registers Mode Setting Configuration Register Sheet 1ROM Control Register Sheet 2 SrompollSerial Preload Sequence Sheet 1 Mode Setting Configuration Register Sheet 2Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Arbiter Control Error RegistersSecondary SERR# Disable Register Primary SERR# Disable RegisterInit Registers Power Management ECP ID and Next Pointer RegisterPM ECP ID APS Power Management Capabilities RegisterDSI PMEPmcsr Bridge Support Extensions Power Management Control and Status RegisterReset Control Register Power Management Data RegisterHS Next Pointer CompactPCI Hot-Swap Control Register Sheet 1CompactPCI Hot-Swap Control Register Sheet 2 Jtag RegistersJtag Instruction Register Options Sheet 1 Bypass Register Jtag Instruction Register Options Sheet 2Boundary-Scan Register Boundary Scan OrderVital Product Data VPD ECP ID and Next Pointer Register VPD RegistersVPD ECP VPD Data Register Vital Product Data VPD Address RegisterPage Acronyms Acronyms CSR Index140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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