Intel 21555 user manual Transaction Ordering Rules

Page 62

PCI Bus Transactions

•A target retry in response to a posted write is allowed, but only due to temporary conditions, such as a buffer-full condition.

The ordering rules apply to transactions crossing the bridge in the same direction.

—A posted write.

—A delayed write and read request.

—A delayed write and read completion.

Delayed completions cross the bridge in the opposite direction of its respective delayed request. Table 16 lists the 21555 transaction ordering rules.

Table 16. 21555 Transaction Ordering Rules

↓ Pass→

Posted

Delayed Read

Delayed Write

Delayed Read

Delayed Write

Write

Request

Request

Completion

Completion

 

 

 

 

 

 

 

Posted Write

No

Yes

Yes

Yes

Yes

 

 

 

 

 

 

Delayed Read

No

Yes/No†

Yes/No†

Yes

Yes

Request

 

 

 

 

 

 

 

 

 

 

 

Delayed Write

No

Yes/No†

Yes/No†

Yes

Yes

Request

 

 

 

 

 

 

 

 

 

 

 

Delayed Read

No

Yes

Yes

Yes

Yes

Completion

 

 

 

 

 

 

 

 

 

 

 

Delayed Write

Yes

Yes

Yes

Yes

Yes

Completion

 

 

 

 

 

 

 

 

 

 

 

†Dependent on the state of the Delayed Transaction Ordering bit.

The only ordering restriction the 21555 enforces is ordering with respect to posted writes. No other transaction other than a delayed write completion can pass a posted write. Posted writes are delivered in the order in which they are accepted.

Delayed transactions may be initiated by the 21555 in any order, and are not necessarily initiated in the order in which they are received. When the 21555 initiates a delayed transaction, the 21555 can do the following:

•When the Delayed Transaction Order Control configuration bit is not set, the 21555 uses a rotating fairness algorithm to select which delayed transaction it initiates next, regardless of the type of target termination is returned (retry, TRDY#, etc.).

•When the Delayed Transaction Order Control configuration bit is set, the 21555 continues to initiate the same transaction until a response other than target retry is received.

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21555 Non-Transparent PCI-to-PCI Bridge User Manual

Page 61 Page 63
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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Figures Tables131 148 108 Page Brief description of the contents of this manual follows PrefaceTerm Words Bytes Bits Data UnitsNumbering Signal Description Type Signal NomenclatureSignal Type Abbreviations STSRegister Abbreviations Access Type DescriptionRegister Abbreviations Introduction Comparing a 21555 to a Transparent PPBCPU PCI Dram PCI ROMCPU PPB Feature Comparison FeatureRegisters Architectural OverviewData Buffers Control LogicMicroarchitecture Primary Bus VGA Support Special ApplicationsProgramming Notes Secondary Bus VGA SupportROM Access Transaction ForwardingPage Group by Signal Pin Description See Signal DescriptionsSignal Pin Functional Groups Signal Name Type Description Primary PCI Bus Interface SignalsPrimary PCI Bus Interface Signals Sheet 1 Preql Primary PCI Bus Interface Signals Sheet 2Ppar PstoplPack64l Primary PCI Bus Interface 64-Bit Extension SignalsPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Pad6332Preq64l Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Ppar64 Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Secondary PCI Bus Interface Signals Sheet 1Sstopl Secondary PCI Bus Interface Signals Sheet 2Spar StrdylSad6332 Secondary PCI Bus Interface 64-Bit Extension SignalsSack64l Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Memory 0 Transaction Address Decoding CSR Address DecodingExpansion ROM Address Mapping Decoding Using the BAR Setup Registers BAR Setup Register ExampleDirect Address Translation Address FormatLookup Table Based Address Translation Direct Offset Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Lookup Table Entry Format Upstream Lookup Table Address TranslationForwarding of 64-Bit Address Memory Transactions Lookup Table Entry FormatI/O Transaction Address Decoding Indirect I/O Transaction GenerationAddress Decoding Subtractive Decoding of I/O Transactions Configuration AccessesType 0 Accesses to 21555 Configuration Space Initiation of Configuration Transactions by Address Decoding Bar Size Address Translation 21555 Bar SummaryBar Summary Page PCI Bus Transactions Transactions OverviewPosted Write Transactions Memory Write Transactions Memory Write and Invalidate TransactionsWrite Performance Tuning Options 3 64-bit Extension Posted Write TransactionWrite-Through Delayed Write Transactions Target Bus Response Initiator Bus Response Delayed Read TransactionsDelayed Write Transaction Target Termination Returns Delayed Read Transaction Target Termination Returns Nonprefetchable ReadsPrefetchable Reads Prefetchable Read Transactions Using the 64-bit ExtensionRead Performance Features and Tuning Options Prefetching Prefetch BoundariesRead Queue Full Threshold Tuning 64-Bit and 32-Bit Transactions Initiated byTarget Terminations Target Terminations Returned byTransaction Termination Errors on the Target Bus Ordering RulesTransaction Ordering Rules PCI Bus Transactions Page Initialization Requirements Power Management, Hot-Swap, and Reset SignalsPower Management, Hot-Swap, and Reset Signals Sheet 1 Spmel Reset BehaviorPower Management, Hot-Swap, and Reset Signals Sheet 2 SrstinlReset Mechanisms PrstlCentral Function During Reset 21555 InitializationWith SROM, Local, and Host Processors Without Serial PreloadWithout Local Processor and Serial Preload Power Management SupportWithout Local Processor Without Host ProcessorNext Power State Action Transitions Between Power Management StatesPower Management Actions 2 PME# SupportOverview of CompactPCI Controller Hardware Interface Power Management Data RegisterCompactPCI Hot-Swap Functionality Primary Lstat K Ω Insertion and Removal ProcessPrstl 332 Ω Initialization Requirements 2a INS ENUM# W DisconnectedW Connected 4b InsertionInitialization Requirements Signal Name Description Primary and Secondary PCI Bus Clock SignalsPrimary and Secondary PCI Bus Clock Signals Sheet 1 ClockingSclk Primary and Secondary PCI Bus Clock Signals Sheet 221555 Secondary Clock Outputs Sclko66 MHz Support Page Interface Signals Parallel ROM InterfaceProm Interface Signals Sheet 1 Signal Type Description NameProm Interface Signals Sheet 2 21555 Prom Read by CSR AccessParallel and Serial ROM Connection WE# OE#Prom Read Timing Prom Write by CSR Access Prom Dword Read Prom Write TimingAccess Time and Strobe Control Read and Write Strobe TimingAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Serial ROM Interface Srom Interface SignalsSrom Interface Signals Sromsrom Preload OperationSrom Configuration Data Preload Format Srom Operation by CSR AccessSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Primary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterPrimary PCI Bus Arbitration Secondary Arbiter Example Bit Name Description Secondary Bus Arbitration Using an External ArbiterArbiter Control Register Interrupt and Scratchpad Registers Primary and Secondary PCI Bus Interrupt SignalsPrimary and Secondary PCI Bus Interrupt Signals Interrupt SupportInterrupt and Scratchpad Registers Doorbell Interrupts Scratchpad RegistersPage Primary PCI Bus Error Signals Error HandlingError Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Type PER † Action Taken Error Transaction Parity ErrorsParity Error Responses Sheet 1 Asserts pperrl Parity Error Responses Sheet 2Error Transaction Parity Error Responses Sheet 3 Asserts sperrlSystem Error SERR# Reporting Jtag Test Port Jtag SignalsJtag Signals Test Access Port Controller InitializationI2O Support Inbound Message PassingI2O Support Outbound Message Passing 116 117 Page VPD Support Reading VPD InformationWriting VPD Information Register Cross Reference Table List of RegistersRegister Summary Theory of Operation Chapter Register Reference InformationByte Reset Value Write Read Configuration RegistersConfiguration Space Address Register Sheet 1 Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Control and Status Registers Configuration Space Address Register Sheet 5Register Name Reset Value Write Access Read Access CSR Address Map Sheet 1CSR Address Map Sheet 2 Ffff W1TC CSR Address Map Sheet 3Ffff W1TS CSR Address Map Sheet 4 CSR Address Map Sheet 5 Address DecodingPrimary and Secondary Address Primary CSR and Downstream Memory 0 Bara Sheet 1Primary CSR and Downstream Memory 0 Bara Sheet 2 Secondary CSR Memory BARsa Sheet 1Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Secondary CSR Memory BARsa Sheet 2Primary and Secondary CSR I/O Barsa Upstream I/O or Memory 0 BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAROffsets Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upper 32 Bits Downstream Memory 3 Bar Upstream Memory 2 BarXlatbase Offsets Downstream I/O or MemoryTranslated Base Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Configuration Transaction Generation Registers Upper 32 Bits Downstream Memory 3 Setup RegisterDownstream and Upstream Configuration Address Registers CfgaddrConfiguration Own Bits Register CfgdataConfiguration CSR Sheet 1 Offset Downstream I/O Address Upstream I/O Address Configuration CSR Sheet 2Downstream I/O Address and Upstream I/O Address Registers Ioaddr IAOffsets Downstream I/O Data Upstream I/O Data Downstream I/O Data and Upstream I/O Data RegistersO Own Bits Registers IodataLutoffset O CSRLookup Table Offset Register Lookup Table Data Register Configuration RegistersPCI Registers Upstream Memory 2 Lookup TableVendor ID Register Primary Interface Configuration Space Address MapSecondary Interface Configuration Space Address Map Device ID RegisterOffsets Primary Command Secondary Command Primary and Secondary Command RegistersPrimary and Secondary Command Registers Sheet 1 SERR# Primary and Secondary Command Registers Sheet 2Primary and Secondary Status Registers Sheet 1 Offsets Primary Status Secondary StatusPrimary and Secondary Status Registers Sheet 2 Revision ID Rev ID RegisterOffsets Primary Class Code Secondary Class Code Primary and Secondary Class Code RegistersPrimary and Secondary Cache Line Size Registers Offsets Primary Cache Line Size Secondary Cache Line SizeOffsets Primary MLT Secondary MLT Header Type RegisterBiST Register Enhanced Capabilities Pointer Register Subsystem Vendor ID RegisterSubsystem ID Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Maximum Latency Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Minimum Grant Registers Chip Control 0 Register Sheet 1 Device-Specific Control and Status RegistersDevice-Specific Control and Status Address Map Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 I20ENA Chip Control 1 Register Sheet 3Chip Status Register 163 Generic Own Bits Register RotsI2O Outbound PostList Interrupt Mask 16.6 I2O RegistersI2O Outbound PostList Status I2O Inbound PostList StatusI2O Outbound Queue I2O Inbound PostList Interrupt MaskI2O Inbound Queue I2OOUT PI2O Outbound FreeList Tail Pointer I2O Inbound FreeList Head PointerI2O Inbound PostList Tail Pointer I2O Outbound PostList Head PointerLdipc W1TLS I2O Inbound PostList CounterI2O Inbound FreeList Counter Ldifc W1TLSLdopc W1TLS I2O Outbound PostList CounterI2O Outbound FreeList Counter Chip Set IRQ Mask Register Interrupt RegistersChip Status CSR PMD0 W1TCPAGE0IRQ W1TC Chip Clear IRQ Mask RegisterUpstream Page Boundary IRQ 0 Register Upstream Page Boundary IRQ Mask 1 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 0 Register Primary Clear IRQ Secondary Clear IRQ Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Set IRQ and Secondary Set IRQ Registers Primary Set IRQPrimary Clear IRQ Mask Secondary Clear IRQ Mask Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Secondary Set IRQ MaskPrimary Expansion ROM BAR Prom RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 2 Primary Expansion ROM Setup Register Sequence onRomdata ROM Setup RegisterROM Data Register Romaddr ROM Address RegisterROM Control Register Sheet 1 ROM Control Register Sheet 2 Mode Setting Configuration Register Sheet 1Srom Registers SrompollByte Description Offset Mode Setting Configuration Register Sheet 2Serial Preload Sequence Sheet 1 Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Error Registers Arbiter ControlPrimary SERR# Disable Register Secondary SERR# Disable RegisterPM ECP ID Power Management ECP ID and Next Pointer RegisterInit Registers DSI Power Management Capabilities RegisterAPS PMEPower Management Control and Status Register Pmcsr Bridge Support ExtensionsPower Management Data Register Reset Control RegisterCompactPCI Hot-Swap Control Register Sheet 1 HS Next PointerJtag Instruction Register Options Sheet 1 Jtag RegistersCompactPCI Hot-Swap Control Register Sheet 2 Boundary-Scan Register Jtag Instruction Register Options Sheet 2Bypass Register Boundary Scan OrderVPD ECP VPD RegistersVital Product Data VPD ECP ID and Next Pointer Register Vital Product Data VPD Address Register VPD Data RegisterPage Acronyms Acronyms Index CSR140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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