Intel 21555 user manual Memory Write Transactions, Memory Write and Invalidate Transactions

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PCI Bus Transactions

5.2.1Memory Write Transactions

As a target, the 21555 disconnects memory write transactions at the following address boundaries:

•An aligned 4KB address boundary.

•An aligned page address boundary for upstream transactions falling in the Upstream Memory 2 address range.

•An aligned cache line boundary, when the MW disconnect bit is set in configuration space.

When the posted write queue fills before the master terminates the transaction, the 21555 returns a target disconnect when the last queue entry is filled. The 21555 does not disconnect on an aligned address boundary, other than those noted in the previous paragraph, when the write queue is almost full. That is, the memory write queue full disconnect condition is optimized for burst length and not alignment.

As an initiator, when the 21555 has posted write data to deliver and the conditions listed in Section 5.2.2 for initiating an MWI transaction are not met, the 21555 uses the memory write command to deliver posted memory write data. The 21555 terminates the memory write burst when the last piece of data in the transaction is delivered, or if the transaction is in flow-through mode, when a queue empty condition is detected. In the latter case, the 21555 master terminates the transaction on the target bus, and then initiates a new transaction when a cache line amount of data is accumulated.

5.2.2Memory Write and Invalidate Transactions

As a target, the 21555 disconnects MWI transactions at the following address boundaries:

•An aligned 4 KB address boundary.

•An aligned page address boundary, for upstream transactions falling in the Upstream Memory 2 address range.

•An aligned cache line boundary, for MWI transactions when less than a cache line of available space remains in the posted write queue.

The 21555 disconnects an MWI on a cache line boundary when less than a cache line remains free in the posted write buffer. This is a different queue full disconnect behavior than that used for the memory write command. In this case, alignment is preserved at the expense of maximizing burst length.

When a master initiates an MWI transaction, it guarantees that it will supply one full cache line of data, or some multiple thereof. The 21555 initiates an MWI transaction on the target bus, regardless of whether the bus command was a memory write or an MWI on the initiator bus, when all of the following conditions are met:

•The MWI Enable bit is set in the Command register corresponding to the target interface.

•The target bus Cache Line Size is set to a valid value (8, 16, or 32 Dwords).

•At least one aligned cache line of data has been posted.

•All byte enables for the posted cache line are turned on.

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Tables Figures131 148 108 Page Preface Brief description of the contents of this manual followsData Units NumberingTerm Words Bytes Bits STS Signal NomenclatureSignal Type Abbreviations Signal Description TypeAccess Type Description Register AbbreviationsRegister Abbreviations Comparing a 21555 to a Transparent PPB IntroductionDram PCI ROM CPUCPU PCI Feature PPB Feature ComparisonControl Logic Architectural OverviewData Buffers RegistersMicroarchitecture Secondary Bus VGA Support Special ApplicationsProgramming Notes Primary Bus VGA SupportTransaction Forwarding ROM AccessPage Signal Descriptions Signal Pin Functional GroupsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Primary PCI Bus Interface Signals Sheet 1Signal Name Type Description Pstopl Primary PCI Bus Interface Signals Sheet 2Ppar PreqlPad6332 Primary PCI Bus Interface 64-Bit Extension SignalsPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Pack64lPad6332 , pcbel74 , and ppar64 to valid logic levels Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Ppar64 Preq64lSecondary PCI Bus Interface Signals Sheet 1 Secondary PCI Bus Interface SignalsStrdyl Secondary PCI Bus Interface Signals Sheet 2Spar SstoplScbel74 Secondary PCI Bus Interface 64-Bit Extension SignalsSack64l Sad6332Miscellaneous Signals Miscellaneous SignalsPage Address Decoding CSR Address Decoding Expansion ROM Address Mapping DecodingMemory 0 Transaction Address Decoding BAR Setup Register Example Using the BAR Setup RegistersAddress Format Direct Address TranslationDirect Offset Address Translation Lookup Table Based Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Upstream Lookup Table Address Translation Lookup Table Entry FormatLookup Table Entry Format Forwarding of 64-Bit Address Memory TransactionsIndirect I/O Transaction Generation I/O Transaction Address DecodingAddress Decoding Configuration Accesses Type 0 Accesses to 21555 Configuration SpaceSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding 21555 Bar Summary Bar SummaryBar Size Address Translation Page Transactions Overview PCI Bus TransactionsPosted Write Transactions Memory Write and Invalidate Transactions Memory Write Transactions3 64-bit Extension Posted Write Transaction Write Performance Tuning OptionsWrite-Through Delayed Write Transactions Delayed Read Transactions Delayed Write Transaction Target Termination ReturnsTarget Bus Response Initiator Bus Response Nonprefetchable Reads Delayed Read Transaction Target Termination ReturnsPrefetchable Read Transactions Using the 64-bit Extension Read Performance Features and Tuning OptionsPrefetchable Reads Prefetch Boundaries Prefetching64-Bit and 32-Bit Transactions Initiated by Read Queue Full Threshold TuningTarget Terminations Returned by Target TerminationsOrdering Rules Transaction Termination Errors on the Target BusTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Power Management, Hot-Swap, and Reset Signals Sheet 1Initialization Requirements Srstinl Reset BehaviorPower Management, Hot-Swap, and Reset Signals Sheet 2 SpmelPrstl Reset Mechanisms21555 Initialization Central Function During ResetWithout Serial Preload With SROM, Local, and Host ProcessorsWithout Host Processor Power Management SupportWithout Local Processor Without Local Processor and Serial Preload2 PME# Support Transitions Between Power Management StatesPower Management Actions Next Power State ActionPower Management Data Register CompactPCI Hot-Swap FunctionalityOverview of CompactPCI Controller Hardware Interface Insertion and Removal Process Prstl 332 ΩPrimary Lstat K Ω Initialization Requirements 4b Insertion W DisconnectedW Connected 2a INS ENUM#Initialization Requirements Clocking Primary and Secondary PCI Bus Clock SignalsPrimary and Secondary PCI Bus Clock Signals Sheet 1 Signal Name DescriptionSclko Primary and Secondary PCI Bus Clock Signals Sheet 221555 Secondary Clock Outputs Sclk66 MHz Support Page Parallel ROM Interface Interface SignalsSignal Type Description Name Prom Interface Signals Sheet 1Prom Interface Signals Sheet 2 WE# OE# Prom Read by CSR AccessParallel and Serial ROM Connection 21555Prom Read Timing Prom Write by CSR Access Prom Write Timing Prom Dword ReadRead and Write Strobe Timing Access Time and Strobe ControlAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Sromsrom Preload Operation Srom Interface SignalsSrom Interface Signals Serial ROM InterfaceSrom Operation by CSR Access Srom Configuration Data Preload FormatSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Secondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsSecondary Bus Arbitration Using the Internal Arbiter Primary PCI Bus ArbitrationSecondary PCI Bus Arbitration Secondary Arbiter Example Secondary Bus Arbitration Using an External Arbiter Arbiter Control RegisterBit Name Description Interrupt Support Primary and Secondary PCI Bus Interrupt SignalsPrimary and Secondary PCI Bus Interrupt Signals Interrupt and Scratchpad RegistersInterrupt and Scratchpad Registers Scratchpad Registers Doorbell InterruptsPage Primary PCI Bus Error Signals Error HandlingError Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Errors Parity Error Responses Sheet 1Type PER † Action Taken Error Transaction Parity Error Responses Sheet 2 Error TransactionAsserts pperrl Asserts sperrl Parity Error Responses Sheet 3System Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Initialization Test Access Port ControllerInbound Message Passing I2O SupportI2O Support Outbound Message Passing 116 117 Page Reading VPD Information VPD SupportWriting VPD Information Theory of Operation Chapter Register Reference Information List of RegistersRegister Summary Register Cross Reference TableRegister Name Preload Hex Access Configuration RegistersConfiguration Space Address Register Sheet 1 Byte Reset Value Write ReadConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 CSR Address Map Sheet 1 Configuration Space Address Register Sheet 5Register Name Reset Value Write Access Read Access Control and Status RegistersCSR Address Map Sheet 2 CSR Address Map Sheet 3 Ffff W1TSFfff W1TC CSR Address Map Sheet 4 Primary CSR and Downstream Memory 0 Bara Sheet 1 Address DecodingPrimary and Secondary Address CSR Address Map Sheet 5Secondary CSR Memory BARsa Sheet 1 Primary CSR and Downstream Memory 0 Bara Sheet 2Secondary CSR Memory BARsa Sheet 2 Primary and Secondary CSR I/O BarsaOffsets Primary CSR I/O BAR Secondary CSR I/O BAR Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR OffsetsUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upstream Memory 2 Bar Upper 32 Bits Downstream Memory 3 BarOffsets Downstream I/O or Memory Translated BaseXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Upper 32 Bits Downstream Memory 3 Setup Register Configuration Transaction Generation RegistersCfgaddr Downstream and Upstream Configuration Address RegistersCfgdata Configuration Own Bits RegisterConfiguration CSR Sheet 1 Ioaddr IA Configuration CSR Sheet 2Downstream I/O Address and Upstream I/O Address Registers Offset Downstream I/O Address Upstream I/O AddressIodata Downstream I/O Data and Upstream I/O Data RegistersO Own Bits Registers Offsets Downstream I/O Data Upstream I/O DataO CSR Lookup Table Offset RegisterLutoffset Upstream Memory 2 Lookup Table Configuration RegistersPCI Registers Lookup Table Data RegisterDevice ID Register Primary Interface Configuration Space Address MapSecondary Interface Configuration Space Address Map Vendor ID RegisterPrimary and Secondary Command Registers Primary and Secondary Command Registers Sheet 1Offsets Primary Command Secondary Command Offsets Primary Status Secondary Status Primary and Secondary Command Registers Sheet 2Primary and Secondary Status Registers Sheet 1 SERR#Revision ID Rev ID Register Primary and Secondary Status Registers Sheet 2Offsets Primary Cache Line Size Secondary Cache Line Size Primary and Secondary Class Code RegistersPrimary and Secondary Cache Line Size Registers Offsets Primary Class Code Secondary Class CodeHeader Type Register BiST RegisterOffsets Primary MLT Secondary MLT Primary and Secondary Interrupt Line Registers Subsystem Vendor ID RegisterSubsystem ID Register Enhanced Capabilities Pointer RegisterPrimary and Secondary Interrupt Pin Registers Primary and Secondary Minimum Grant RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Registers Device-Specific Control and Status Address MapChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Control 1 Register Sheet 3 Chip Status RegisterI20ENA 163 Rots Generic Own Bits RegisterI2O Inbound PostList Status 16.6 I2O RegistersI2O Outbound PostList Status I2O Outbound PostList Interrupt MaskI2OOUT P I2O Inbound PostList Interrupt MaskI2O Inbound Queue I2O Outbound QueueI2O Outbound PostList Head Pointer I2O Inbound FreeList Head PointerI2O Inbound PostList Tail Pointer I2O Outbound FreeList Tail PointerLdifc W1TLS I2O Inbound PostList CounterI2O Inbound FreeList Counter Ldipc W1TLSI2O Outbound PostList Counter I2O Outbound FreeList CounterLdopc W1TLS PMD0 W1TC Interrupt RegistersChip Status CSR Chip Set IRQ Mask RegisterChip Clear IRQ Mask Register Upstream Page Boundary IRQ 0 RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ 1 Register Upstream Page Boundary IRQ Mask 0 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Set IRQ Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Set IRQ and Secondary Set IRQ Registers Primary Clear IRQ Secondary Clear IRQSecondary Set IRQ Mask Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Primary Clear IRQ Mask Secondary Clear IRQ MaskProm Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 2Primary Expansion ROM BAR Sequence on Primary Expansion ROM Setup RegisterROM Setup Register ROM Data RegisterRomdata ROM Address Register ROM Control Register Sheet 1Romaddr Srompoll Mode Setting Configuration Register Sheet 1Srom Registers ROM Control Register Sheet 2Mode Setting Configuration Register Sheet 2 Serial Preload Sequence Sheet 1Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Arbiter Control Error RegistersSecondary SERR# Disable Register Primary SERR# Disable RegisterPower Management ECP ID and Next Pointer Register Init RegistersPM ECP ID PME Power Management Capabilities RegisterAPS DSIPmcsr Bridge Support Extensions Power Management Control and Status RegisterReset Control Register Power Management Data RegisterHS Next Pointer CompactPCI Hot-Swap Control Register Sheet 1Jtag Registers CompactPCI Hot-Swap Control Register Sheet 2Jtag Instruction Register Options Sheet 1 Boundary Scan Order Jtag Instruction Register Options Sheet 2Bypass Register Boundary-Scan RegisterVPD Registers Vital Product Data VPD ECP ID and Next Pointer RegisterVPD ECP VPD Data Register Vital Product Data VPD Address RegisterPage Acronyms Acronyms CSR Index140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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