Intel 21555 user manual Primary SERR# Disable Register, Secondary SERR# Disable Register

Page 184

List of Registers

Table 116. Primary SERR# Disable Register

This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert p_serr_l for a particular condition. When the bit is a 0, the assertion of p_serr_l is not masked for this event.

When the bit is a 1, the assertion of p_serr_l is masked for this event.

•Primary byte offset: D4h

•Secondary byte offset: D4h

Bit

Name

R/W

Description

 

 

 

 

 

Downstream

 

Disables p_serr_l assertion when a downstream master time-out condition

 

Delayed

 

0

Transaction

R/W

is detected and the downstream transaction is discarded.

 

Master

 

Reset value is 0

 

Time-out

 

 

 

 

 

 

 

Downstream

 

Disables p_serr_l assertion when 21555 discards a downstream delayed

1

Delayed Read

R/W

read transaction request after receiving 224 target retries from secondary bus

Transaction

target.

 

 

 

Discarded

 

Reset value is 0

 

 

 

 

 

Downstream

 

Disables p_serr_l assertion when 21555 discards a downstream delayed

2

Delayed Write

R/W

write transaction request after receiving 224 target retries from secondary

Transaction

bus target.

 

 

 

Discarded

 

Reset value is 0

 

 

 

 

 

Downstream

 

Disables p_serr_l assertion when 21555 discards a downstream posted

3

Posted Write

R/W

write transaction after receiving 224 target retries from secondary bus target.

 

Data Discarded

 

Reset value is 0

 

 

 

 

 

Target Abort

 

Disables p_serr_l assertion when 21555 detects a target abort on the

 

during

 

4

R/W

secondary interface in response to a downstream posted write.

Downstream

 

 

Reset value is 0

 

Posted Write

 

 

 

 

 

 

 

 

 

Master Abort

 

Disables p_serr_l assertion when the 21555 detects a master abort on the

 

during

 

5

R/W

secondary interface when initiating a downstream posted write.

Downstream

 

 

Reset value is 0

 

Posted Write

 

 

 

 

 

 

 

 

 

Downstream

 

Disables p_serr_l assertion when the 21555 detects s_perr_l asserted

6

Posted Write

R/W

during a downstream posted write.

 

Parity Error

 

Reset value is 0

 

 

 

 

7

Reserved

R

Reserved. Returns 0 when read.

 

 

 

 

Table 117. Secondary SERR# Disable Register

This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert s_serr_l for a particular condition. When the bit is a 0, the assertion of s_serr_l is not masked for this event.

When the bit is a 1, the assertion of s_serr_l is masked for this event.

•Primary byte offset: D5h

•Secondary byte offset: D5h

Bit

Name

R/W

Description

 

 

 

 

 

Upstream Delayed

 

Disables s_serr_l assertion when an upstream master timeout

0

Transaction Master

R/W

condition is detected and the upstream transaction is discarded.

 

Timeout

 

Reset value is 0

 

 

 

 

184

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Contents Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Figures Tables131 148 108 Page Brief description of the contents of this manual follows PrefaceNumbering Data UnitsTerm Words Bytes Bits Signal Nomenclature Signal Type AbbreviationsSignal Description Type STSRegister Abbreviations Access Type DescriptionRegister Abbreviations Introduction Comparing a 21555 to a Transparent PPBCPU Dram PCI ROMCPU PCI PPB Feature Comparison FeatureArchitectural Overview Data BuffersRegisters Control LogicMicroarchitecture Special Applications Programming NotesPrimary Bus VGA Support Secondary Bus VGA SupportROM Access Transaction ForwardingPage Signal Pin Functional Groups Signal DescriptionsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Sheet 1 Primary PCI Bus Interface SignalsSignal Name Type Description Primary PCI Bus Interface Signals Sheet 2 PparPreql PstoplPrimary PCI Bus Interface 64-Bit Extension Signals Primary PCI Bus Interface 64-Bit Extension Signals Sheet 1Pack64l Pad6332Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2 Ppar64Preq64l Pad6332 , pcbel74 , and ppar64 to valid logic levelsSecondary PCI Bus Interface Signals Secondary PCI Bus Interface Signals Sheet 1Secondary PCI Bus Interface Signals Sheet 2 SparSstopl StrdylSecondary PCI Bus Interface 64-Bit Extension Signals Sack64lSad6332 Scbel74Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Expansion ROM Address Mapping Decoding CSR Address DecodingMemory 0 Transaction Address Decoding Using the BAR Setup Registers BAR Setup Register ExampleDirect Address Translation Address FormatLookup Table Based Address Translation Direct Offset Address TranslationUpstream Memory 2 Window Size Address Translation Using a Lookup Table Lookup Table Entry Format Upstream Lookup Table Address TranslationForwarding of 64-Bit Address Memory Transactions Lookup Table Entry FormatI/O Transaction Address Decoding Indirect I/O Transaction GenerationAddress Decoding Type 0 Accesses to 21555 Configuration Space Configuration AccessesSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding Bar Summary 21555 Bar SummaryBar Size Address Translation Page PCI Bus Transactions Transactions OverviewPosted Write Transactions Memory Write Transactions Memory Write and Invalidate TransactionsWrite Performance Tuning Options 3 64-bit Extension Posted Write TransactionWrite-Through Delayed Write Transactions Delayed Write Transaction Target Termination Returns Delayed Read TransactionsTarget Bus Response Initiator Bus Response Delayed Read Transaction Target Termination Returns Nonprefetchable ReadsRead Performance Features and Tuning Options Prefetchable Read Transactions Using the 64-bit ExtensionPrefetchable Reads Prefetching Prefetch BoundariesRead Queue Full Threshold Tuning 64-Bit and 32-Bit Transactions Initiated byTarget Terminations Target Terminations Returned byTransaction Termination Errors on the Target Bus Ordering RulesTransaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Sheet 1 Power Management, Hot-Swap, and Reset SignalsInitialization Requirements Reset Behavior Power Management, Hot-Swap, and Reset Signals Sheet 2Spmel SrstinlReset Mechanisms PrstlCentral Function During Reset 21555 InitializationWith SROM, Local, and Host Processors Without Serial PreloadPower Management Support Without Local ProcessorWithout Local Processor and Serial Preload Without Host ProcessorTransitions Between Power Management States Power Management ActionsNext Power State Action 2 PME# SupportCompactPCI Hot-Swap Functionality Power Management Data RegisterOverview of CompactPCI Controller Hardware Interface Prstl 332 Ω Insertion and Removal ProcessPrimary Lstat K Ω Initialization Requirements W Disconnected W Connected2a INS ENUM# 4b InsertionInitialization Requirements Primary and Secondary PCI Bus Clock Signals Primary and Secondary PCI Bus Clock Signals Sheet 1Signal Name Description ClockingPrimary and Secondary PCI Bus Clock Signals Sheet 2 21555 Secondary Clock OutputsSclk Sclko66 MHz Support Page Interface Signals Parallel ROM InterfaceProm Interface Signals Sheet 1 Signal Type Description NameProm Interface Signals Sheet 2 Prom Read by CSR Access Parallel and Serial ROM Connection21555 WE# OE#Prom Read Timing Prom Write by CSR Access Prom Dword Read Prom Write TimingAccess Time and Strobe Control Read and Write Strobe TimingAttaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Srom Interface Signals Srom Interface SignalsSerial ROM Interface Sromsrom Preload OperationSrom Configuration Data Preload Format Srom Operation by CSR AccessSerial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Primary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Signals Secondary PCI Bus Arbitration SignalsPrimary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterSecondary PCI Bus Arbitration Secondary Arbiter Example Arbiter Control Register Secondary Bus Arbitration Using an External ArbiterBit Name Description Primary and Secondary PCI Bus Interrupt Signals Primary and Secondary PCI Bus Interrupt SignalsInterrupt and Scratchpad Registers Interrupt SupportInterrupt and Scratchpad Registers Doorbell Interrupts Scratchpad RegistersPage Error Handling Error SignalsPrimary PCI Bus Error Signals Primary PCI Bus Error SignalsSecondary PCI Bus Error Signals Parity Error Responses Sheet 1 Parity ErrorsType PER † Action Taken Error Transaction Error Transaction Parity Error Responses Sheet 2Asserts pperrl Parity Error Responses Sheet 3 Asserts sperrlSystem Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Test Access Port Controller InitializationI2O Support Inbound Message PassingI2O Support Outbound Message Passing 116 117 Page VPD Support Reading VPD InformationWriting VPD Information List of Registers Register SummaryRegister Cross Reference Table Theory of Operation Chapter Register Reference InformationConfiguration Registers Configuration Space Address Register Sheet 1Byte Reset Value Write Read Register Name Preload Hex AccessConfiguration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 Configuration Space Address Register Sheet 5 Register Name Reset Value Write Access Read AccessControl and Status Registers CSR Address Map Sheet 1CSR Address Map Sheet 2 Ffff W1TS CSR Address Map Sheet 3Ffff W1TC CSR Address Map Sheet 4 Address Decoding Primary and Secondary AddressCSR Address Map Sheet 5 Primary CSR and Downstream Memory 0 Bara Sheet 1Primary CSR and Downstream Memory 0 Bara Sheet 2 Secondary CSR Memory BARsa Sheet 1Primary and Secondary CSR I/O Barsa Secondary CSR Memory BARsa Sheet 2Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Offsets Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BARUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upper 32 Bits Downstream Memory 3 Bar Upstream Memory 2 BarTranslated Base Offsets Downstream I/O or MemoryXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Configuration Transaction Generation Registers Upper 32 Bits Downstream Memory 3 Setup RegisterDownstream and Upstream Configuration Address Registers CfgaddrConfiguration Own Bits Register CfgdataConfiguration CSR Sheet 1 Configuration CSR Sheet 2 Downstream I/O Address and Upstream I/O Address RegistersOffset Downstream I/O Address Upstream I/O Address Ioaddr IADownstream I/O Data and Upstream I/O Data Registers O Own Bits RegistersOffsets Downstream I/O Data Upstream I/O Data IodataLookup Table Offset Register O CSRLutoffset Configuration Registers PCI RegistersLookup Table Data Register Upstream Memory 2 Lookup TablePrimary Interface Configuration Space Address Map Secondary Interface Configuration Space Address MapVendor ID Register Device ID RegisterPrimary and Secondary Command Registers Sheet 1 Primary and Secondary Command RegistersOffsets Primary Command Secondary Command Primary and Secondary Command Registers Sheet 2 Primary and Secondary Status Registers Sheet 1SERR# Offsets Primary Status Secondary StatusPrimary and Secondary Status Registers Sheet 2 Revision ID Rev ID RegisterPrimary and Secondary Class Code Registers Primary and Secondary Cache Line Size RegistersOffsets Primary Class Code Secondary Class Code Offsets Primary Cache Line Size Secondary Cache Line SizeBiST Register Header Type RegisterOffsets Primary MLT Secondary MLT Subsystem Vendor ID Register Subsystem ID RegisterEnhanced Capabilities Pointer Register Primary and Secondary Interrupt Line RegistersPrimary and Secondary Minimum Grant Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Address Map Device-Specific Control and Status RegistersChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Status Register Chip Control 1 Register Sheet 3I20ENA 163 Generic Own Bits Register Rots16.6 I2O Registers I2O Outbound PostList StatusI2O Outbound PostList Interrupt Mask I2O Inbound PostList StatusI2O Inbound PostList Interrupt Mask I2O Inbound QueueI2O Outbound Queue I2OOUT PI2O Inbound FreeList Head Pointer I2O Inbound PostList Tail PointerI2O Outbound FreeList Tail Pointer I2O Outbound PostList Head PointerI2O Inbound PostList Counter I2O Inbound FreeList CounterLdipc W1TLS Ldifc W1TLSI2O Outbound FreeList Counter I2O Outbound PostList CounterLdopc W1TLS Interrupt Registers Chip Status CSRChip Set IRQ Mask Register PMD0 W1TCUpstream Page Boundary IRQ 0 Register Chip Clear IRQ Mask RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ Mask 0 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Clear IRQ and Secondary Clear IRQ Registers Primary Set IRQ and Secondary Set IRQ RegistersPrimary Clear IRQ Secondary Clear IRQ Primary Set IRQPrimary Set IRQ Mask and Secondary Set IRQ Mask Registers Scratchpad 0 Through Scratchpad 7 Registers Sheet 1Primary Clear IRQ Mask Secondary Clear IRQ Mask Secondary Set IRQ MaskScratchpad 0 Through Scratchpad 7 Registers Sheet 2 Prom RegistersPrimary Expansion ROM BAR Primary Expansion ROM Setup Register Sequence onROM Data Register ROM Setup RegisterRomdata ROM Control Register Sheet 1 ROM Address RegisterRomaddr Mode Setting Configuration Register Sheet 1 Srom RegistersROM Control Register Sheet 2 SrompollSerial Preload Sequence Sheet 1 Mode Setting Configuration Register Sheet 2Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Error Registers Arbiter ControlPrimary SERR# Disable Register Secondary SERR# Disable RegisterInit Registers Power Management ECP ID and Next Pointer RegisterPM ECP ID Power Management Capabilities Register APSDSI PMEPower Management Control and Status Register Pmcsr Bridge Support ExtensionsPower Management Data Register Reset Control RegisterCompactPCI Hot-Swap Control Register Sheet 1 HS Next PointerCompactPCI Hot-Swap Control Register Sheet 2 Jtag RegistersJtag Instruction Register Options Sheet 1 Jtag Instruction Register Options Sheet 2 Bypass RegisterBoundary-Scan Register Boundary Scan OrderVital Product Data VPD ECP ID and Next Pointer Register VPD RegistersVPD ECP Vital Product Data VPD Address Register VPD Data RegisterPage Acronyms Acronyms Index CSR140
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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