Intel 80960HT, 80960HD manual Hx Processor Family Pin Descriptions Sheet 1, Name Type Description

Page 16

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)

 

Name

 

Type

Description

 

 

 

 

 

 

 

 

 

 

 

 

O

ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most

 

 

 

 

 

significant address bit and A2 is the least significant. During a bus access, A31:2

 

A31:2

 

H(Z)

 

 

identify all external addresses to word (4-byte) boundaries. The byte enable

 

 

B(Z)

 

 

 

 

 

signals indicate the selected byte in each word. During burst accesses, A3 and

 

 

 

 

 

R(Z)

 

 

 

 

 

A2 increment to indicate successive addresses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width

 

 

 

 

 

S(L)

 

D31:0

 

configuration. The least significant bit of the data is carried on D0 and the most

 

 

H(Z)

 

 

significant on D31. The lower eight data lines (D7:0) are used when the bus is

 

 

 

 

 

B(Z)

 

 

 

 

 

configured for 8-bit data. When configured for 16-bit data, D15:0 are used.

 

 

 

 

 

R(Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA PARITY carries parity information for the data bus. Each parity bit is

 

 

 

 

 

 

assigned a group of eight data bus pins as follows:

 

 

 

 

 

I/O

DP3 generates/checks parity for D31:24

 

DP3:0

 

S(L)

DP2 generates/checks parity for D23:16

 

 

H(Z)

DP1 generates/checks parity for D15:8

 

 

 

 

 

B(Z)

DP0 generates/checks parity for D7:0

 

 

 

 

 

R(Z)

Parity information is generated for a processor write cycle and is checked for a

 

 

 

 

 

 

processor read cycle. Parity checking and polarity are programmable. Parity

 

 

 

 

 

 

generation/checking is only performed for the size of the data accessed.

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

H(Q)

PARITY CHECK indicates the result of a parity check operation. An asserted

 

PCHK

 

 

B(Q)

PCHK indicates that the previous bus read access resulted in a parity check error.

 

 

 

 

 

 

 

 

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BYTE ENABLES select which of the four bytes addressed by A31:2 are active

 

 

 

 

 

 

during a bus access. Byte enable encoding is dependent on the bus width of the

 

 

 

 

 

 

memory region accessed:

 

 

 

 

 

 

32-bit bus:

 

 

 

 

 

 

BE3 enables D31:24

 

 

 

 

 

 

BE2 enables D23:16

 

 

 

 

 

O

BE1 enables D15:8

 

 

 

 

 

BE0 enables D7:0

 

 

 

 

 

H(Z)

16-bit bus:

 

BE3:0

 

 

B(Z)

BE3 becomes Byte High Enable (enables D15:8)

 

 

 

 

 

 

 

 

 

 

R(1)

BE2 is not used (state is undefined)

 

 

 

 

 

 

BE1 becomes Address Bit 1 (A1)

 

 

 

 

 

 

BE0 becomes Byte Low Enable (enables D7:0)

 

 

 

 

 

 

8-bit bus:

 

 

 

 

 

 

BE3 is not used (state is undefined)

 

 

 

 

 

 

BE2 is not used (state is undefined)

 

 

 

 

 

 

BE1 Address Bit 1 (A1)

 

 

 

 

 

 

BE0 Address Bit 0 (A0)

 

 

 

 

 

 

 

 

 

 

 

 

O

WRITE/READ is low for read accesses and high for write accesses.

 

 

 

 

 

W/R becomes valid during the address phase of a bus cycle and remains valid

 

 

 

 

 

H(Z)

until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/

 

W/R

 

 

 

R changes state when the next address is presented.

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

0= Read

 

 

 

 

 

R(0)

 

 

 

 

 

 

1= Write

 

 

 

 

 

 

 

 

 

 

 

 

O

DATA/CODE indicates that a bus access is a data access or an instruction

 

 

 

 

 

H(Z)

access. D/C has the same timing as W/R.

 

D/C

 

 

 

0 = Code

 

 

B(Z)

 

 

 

 

 

 

 

 

 

 

R(0)

1 = Data

 

 

 

 

 

 

 

16

Datasheet

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Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables Date History80960Hx AC Characteristics on Date Revision HistoryThis page intentionally left blank Hx Product Description Product Core Voltage Operating Frequency bus/coreKey 80960Hx Features I960 Processor FamilyOn-Chip Caches and Data RAM Fail Codes For Bist bit 7 = Bit When SetRemaining Fail Codes bit 7 = Comparison Branch Call/Return Fault Instruction Set SummaryHx Instruction Set Data Movement Arithmetic Logical Bit / Bit Field / ByteHA/HD/HT Package Types and Speeds Package/Name Device Core Speed Bus Speed Order # MHzPin Descriptions Symbol DescriptionPin Description Nomenclature Hx Processor Family Pin Descriptions Sheet 1 Name Type DescriptionHx Processor Family Pin Descriptions Sheet 2 SUPHx Processor Family Pin Descriptions Sheet 3 HoldHx Processor Family Pin Descriptions Sheet 4 ClkinHx 168-Pin PGA Pinout- View from Top Pins Facing Down 80960Hx Mechanical DataHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Signal Name Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1Pin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Package Thermal Specifications Equation 1. Calculation of Ambient Temperature TAHx 168-Pin PGA Package Thermal Characteristics Maximum TA at Various Airflows in C PGA Package OnlyAirflow-ft/min m/sec 600Hx 208-Pin PQ4 Package Thermal Characteristics Maximum TA at Various Airflows in C PQ4 Package OnlyThermal Resistance C/Watt Airflow ft./min m/sec Parameter 400Heat Sink Adhesives PowerQuad4 Plastic PackageStepping Register Information Hx Device ID Model Types Fields of 80960Hx Device IDDevice ID Version Numbers for Different Steppings Sources for Accessories SocketsAbsolute Maximum Ratings Operating ConditionsAbsolute Maximum Ratings Operating ConditionsRecommended Connections VCC5 Pin Requirements VdiffVccpll Pin Requirements Sym Parameter Min Max UnitsHx D.C. Characteristics Sheet 1 D.C.SpecificationsSymbol Parameter Min Typ Max Units Hx D.C. Characteristics Sheet 2A.C. Specifications Hx A.C. Characteristics Sheet 1Symbol Parameter Min Max Units Input Clock 1 Synchronous Outputs 1, 2, 3Relative Output Timings 1, 2, 3, 6 Hx A.C. Characteristics Sheet 2Relative Input Timings 1, 7 C. Characteristics Notes Hx Boundary Scan Test Signal Timings1 A.C. Test Conditions A.C. Timing Waveforms Clkin WaveformOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Once Mode Reset OnceNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States Hx Boundary Scan Chain Sheet 1 80960Hx Boundary Scan ChainBoundary Scan Cell Cell Type Comment Hx Boundary Scan Chain Sheet 2 LockbarHx Boundary Scan Chain Sheet 3 NmibarHx Boundary Scan Chain Sheet 4 PchkBoundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
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