Intel 80960HD, 80960HT Hx Product Description, Product Core Voltage Operating Frequency bus/core

Page 9

80960HA/HD/HT

1.0About This Document

This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics, other than parametric performance, are published in the i960® Hx Microprocessor User’s Guide (272484).

In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table 1. Throughout this document, information that is specific to each is clearly indicated.

Figure 1. 80960Hx Block Diagram

 

 

Instruction Prefetch Queue

Guarded Memory Unit

Control

 

 

 

 

 

 

JTAG Port

Instruction Cache

Memory Region Configuration

 

 

 

16 Kbyte, Four-Way Set-Associative

Address

 

 

Bus Controller

 

Timers

 

 

 

128-Bit Cache Bus

 

 

 

 

 

 

Bus Request Queues

Data

Interrupt

Programmable

 

 

Parallel Instruction Scheduler

 

 

Port

Interrupt Controller

Data Cache

 

 

 

 

8 Kbyte, Four-Way Set-Associative

 

 

 

 

 

 

 

Multiply/Divide Unit

 

 

Data RAM - 2 Kbyte

 

 

 

Register-Side

Memory-Side

 

 

Execution Unit

 

 

 

Machine Bus

Machine Bus

Register Cache - 5 to 15 sets

 

 

 

 

 

 

Six-Port Register File

Address Generation Unit

 

 

 

64-bit SRC1 Bus

32-bit Base Bus

 

 

 

 

 

 

 

64-bit SRC2 Bus

128-bit Load Bus

 

 

 

 

64-bit DST Bus

128-bit Store Bus

 

 

2.0Intel 80960Hx Processor

The Intel 80960Hx processor provides new performance levels while maintaining backward compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. This is accomplished by providing processors that may run at the bus speed or faster using Intel’s clock multiplying technology (see Table 1). The 80960Hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock. The 80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external bus speed.

Table 1. 80960Hx Product Description

Product

Core

Voltage

Operating Frequency (bus/core)

 

 

 

 

80960HA

1x

3.3 V†

25/25, 33/33, 40/40

80960HD

2x

3.3 V†

25/50, 33/66, 40/80

80960HT

3x

3.3 V†

25/75

†Processor inputs are 5 V tolerant.

1.The 80960Hx is not “ drop-in” compatible in an 80960Cx-based system. Customers may design systems that accept either 80960Hx or Cx processors.

Datasheet

9

Page 8 Page 10
Image 9
Page 8 Page 10
Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables History DateDate Revision History 80960Hx AC Characteristics onThis page intentionally left blank Product Core Voltage Operating Frequency bus/core Hx Product DescriptionI960 Processor Family Key 80960Hx FeaturesOn-Chip Caches and Data RAM Bit When Set Fail Codes For Bist bit 7 =Remaining Fail Codes bit 7 = Instruction Set Summary Comparison Branch Call/Return FaultHx Instruction Set Data Movement Arithmetic Logical Bit / Bit Field / BytePackage/Name Device Core Speed Bus Speed Order # MHz HA/HD/HT Package Types and SpeedsSymbol Description Pin DescriptionsPin Description Nomenclature Name Type Description Hx Processor Family Pin Descriptions Sheet 1SUP Hx Processor Family Pin Descriptions Sheet 2Hold Hx Processor Family Pin Descriptions Sheet 3Clkin Hx Processor Family Pin Descriptions Sheet 480960Hx Mechanical Data Hx 168-Pin PGA Pinout- View from Top Pins Facing DownHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1 Signal NamePin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Equation 1. Calculation of Ambient Temperature TA Package Thermal SpecificationsMaximum TA at Various Airflows in C PGA Package Only Hx 168-Pin PGA Package Thermal CharacteristicsAirflow-ft/min m/sec 600Maximum TA at Various Airflows in C PQ4 Package Only Hx 208-Pin PQ4 Package Thermal CharacteristicsThermal Resistance C/Watt Airflow ft./min m/sec Parameter 400PowerQuad4 Plastic Package Heat Sink AdhesivesStepping Register Information Fields of 80960Hx Device ID Hx Device ID Model TypesDevice ID Version Numbers for Different Steppings Sockets Sources for AccessoriesOperating Conditions Absolute Maximum RatingsAbsolute Maximum Ratings Operating ConditionsVCC5 Pin Requirements Vdiff Recommended ConnectionsSym Parameter Min Max Units Vccpll Pin RequirementsD.C.Specifications Hx D.C. Characteristics Sheet 1Symbol Parameter Min Typ Max Units Sheet 2 Hx D.C. CharacteristicsHx A.C. Characteristics Sheet 1 A.C. SpecificationsSymbol Parameter Min Max Units Input Clock 1 Synchronous Outputs 1, 2, 3Hx A.C. Characteristics Sheet 2 Relative Output Timings 1, 2, 3, 6Relative Input Timings 1, 7 Hx Boundary Scan Test Signal Timings C. Characteristics Notes1 A.C. Test Conditions Clkin Waveform A.C. Timing WaveformsOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Reset Once Once ModeNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States 80960Hx Boundary Scan Chain Hx Boundary Scan Chain Sheet 1Boundary Scan Cell Cell Type Comment Lockbar Hx Boundary Scan Chain Sheet 2Nmibar Hx Boundary Scan Chain Sheet 3Pchk Hx Boundary Scan Chain Sheet 4Boundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
Top Page Image Contents