Intel 80960HA, 80960HD, 80960HT manual Recommended Connections, VCC5 Pin Requirements Vdiff

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80960HA/HD/HT

4.3Recommended Connections

Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960Hx-based circuit board should include power (VCC) and ground (VSS) planes for power distribution. Every VCC pin must be connected to the power plane; every VSS pin must be connected to the ground plane. Pins identified as “ NC” — no connect pins— must not be connected in the system.

Liberal decoupling capacitance should be placed near the 80960Hx. The processor may cause transient power surges when its output buffers transition, particularly when connected to large capacitive loads.

Low inductance capacitors and interconnects are recommended for best high-frequency electrical performance. Inductance may be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages offer the lowest possible inductance.

For reliable operation, always connect unused inputs to an appropriate signal level. In particular, any unused interrupt (XINT7:0, NMI) input should be connected to VCC through a pull-up resistor, as should BTERM when not used. Pull-up resistors should be in the range of 20 KΩ for each pin tied high. When READY or HOLD are not used, the unused input should be connected to ground.

N.C. pins must always remain unconnected.

4.4VCC5 Pin Requirements (VDIFF)

In mixed-voltage systems that drive 80960Hx processor inputs in excess of 3.3 V, the VCC5 pin must be connected to the system’s 5 V supply. To limit current flow into the VCC5 pin, there is a limit to the voltage differential between the VCC5 pin and the other VCC pins. The voltage differential between the 80960Hx VCC5 pin and its 3.3 V VCC pins should never exceed 2.25 V. This limit applies to power-up, power-down, and steady-state operation. Table 21 outlines this requirement.

Meeting this requirement ensures proper operation and ensures that the current draw into the VCC5 pin does not exceed the ICC5 specification.

When the voltage difference requirements cannot be met due to system design limitations, an alternate solution may be employed. As shown in Figure 7, a minimum of 100 Ω series resistor may be used to limit the current into the VCC5 pin. This resistor ensures that current drawn by the VCC5 pin does not exceed the maximum rating for this pin.

Figure 7. VCC5 Current-Limiting Resistor

+5 V (±0.25 V)

VCC5 Pin

 

 

 

100 Ω (±5%, 0.5 W)

This resistor is not necessary in systems that may ensure the VDIFF specification.

In 3.3 V-only systems and systems that drive 80960Hx pins from 3.3 V logic, connect the VCC5 pin directly to the 3.3 V VCC plane.

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Datasheet

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Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables Date History80960Hx AC Characteristics on Date Revision HistoryThis page intentionally left blank Hx Product Description Product Core Voltage Operating Frequency bus/coreKey 80960Hx Features I960 Processor FamilyOn-Chip Caches and Data RAM Remaining Fail Codes bit 7 = Bit When SetFail Codes For Bist bit 7 = Hx Instruction Set Comparison Branch Call/Return FaultInstruction Set Summary Data Movement Arithmetic Logical Bit / Bit Field / ByteHA/HD/HT Package Types and Speeds Package/Name Device Core Speed Bus Speed Order # MHzPin Description Nomenclature Symbol DescriptionPin Descriptions Hx Processor Family Pin Descriptions Sheet 1 Name Type DescriptionHx Processor Family Pin Descriptions Sheet 2 SUPHx Processor Family Pin Descriptions Sheet 3 HoldHx Processor Family Pin Descriptions Sheet 4 ClkinHx 168-Pin PGA Pinout- View from Top Pins Facing Down 80960Hx Mechanical DataHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Pin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1Signal Name Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Package Thermal Specifications Equation 1. Calculation of Ambient Temperature TAAirflow-ft/min m/sec Hx 168-Pin PGA Package Thermal CharacteristicsMaximum TA at Various Airflows in C PGA Package Only 600Thermal Resistance C/Watt Airflow ft./min m/sec Parameter Hx 208-Pin PQ4 Package Thermal CharacteristicsMaximum TA at Various Airflows in C PQ4 Package Only 400Stepping Register Information PowerQuad4 Plastic PackageHeat Sink Adhesives Device ID Version Numbers for Different Steppings Fields of 80960Hx Device IDHx Device ID Model Types Sources for Accessories SocketsAbsolute Maximum Ratings Absolute Maximum RatingsOperating Conditions Operating ConditionsRecommended Connections VCC5 Pin Requirements VdiffVccpll Pin Requirements Sym Parameter Min Max UnitsSymbol Parameter Min Typ Max Units D.C.SpecificationsHx D.C. Characteristics Sheet 1 Hx D.C. Characteristics Sheet 2Symbol Parameter Min Max Units Input Clock 1 A.C. SpecificationsHx A.C. Characteristics Sheet 1 Synchronous Outputs 1, 2, 3Relative Input Timings 1, 7 Hx A.C. Characteristics Sheet 2Relative Output Timings 1, 2, 3, 6 C. Characteristics Notes Hx Boundary Scan Test Signal Timings1 A.C. Test Conditions A.C. Timing Waveforms Clkin WaveformOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Once Mode Reset OnceNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States Boundary Scan Cell Cell Type Comment 80960Hx Boundary Scan ChainHx Boundary Scan Chain Sheet 1 Hx Boundary Scan Chain Sheet 2 LockbarHx Boundary Scan Chain Sheet 3 NmibarHx Boundary Scan Chain Sheet 4 PchkBoundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
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