Intel 80960HD, 80960HT, 80960HA manual Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1

Page 24

80960HA/HD/HT

Table 9. 80960Hx 168-Pin PGA Pinout— Pin Number Order (Sheet 1 of 2)

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

PGA

Signal Name

Pin

Pin

Pin

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

VSS

B14

 

 

 

NC

E15

VCC

K15

VSS

A2

 

 

 

 

 

 

 

 

 

 

B15

 

 

 

 

 

 

 

E16

A4

K16

VCC

 

 

 

FAIL

 

 

 

 

 

 

 

 

XINT0

 

 

A3

 

 

 

DP0

B16

 

 

 

 

 

 

 

E17

A5

K17

A11

 

 

 

 

XINT3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

 

 

DP2

B17

 

 

 

 

 

 

 

F1

D8

L1

D15

 

 

 

 

XINT5

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

VOLDET

C1

 

 

 

D3

F2

D6

L2

D14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

 

 

 

C2

 

 

 

D1

F3

VCC

L3

VSS

 

 

TRST

 

 

 

 

 

 

 

 

A7

 

 

 

TDI

C3

 

 

 

 

 

 

 

F15

VSS

L15

VSS

 

 

 

 

ONCE

 

A8

 

 

TDO

C4

 

 

 

VSS

F16

VCC

L16

A13

A9

 

 

 

NC

C5

 

 

VCC5

F17

A6

L17

A12

 

 

 

 

 

 

 

 

 

 

 

 

 

A10

 

 

 

NC

C6

 

 

VCC

G1

D9

M1

D16

A11

 

 

 

CT0

C7

 

 

 

VSS

G2

VCC

M2

VCC

A12

 

 

 

CT1

C8

 

 

 

VSS

G3

VSS

M3

VSS

A13

 

 

 

CT2

C9

 

 

 

VSS

G15

VSS

M15

VSS

A14

 

 

 

CT3

C10

 

 

 

VSS

G16

A7

M16

VCC

A15

 

 

 

 

 

 

 

 

 

 

C11

 

 

 

VSS

G17

A8

M17

A14

 

 

XINT1

 

 

 

 

 

A16

 

 

 

 

 

 

 

 

 

 

C12

 

 

 

VSS

H1

D11

N1

D17

 

RESET

 

 

 

 

A17

 

 

 

 

 

 

 

 

 

 

C13

CLKIN

H2

D10

N2

D18

 

 

XINT2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B1

 

 

 

 

 

 

 

 

 

 

C14

 

 

VCC

H3

VSS

N3

VCC

 

 

BOFF

 

 

 

 

B2

 

STEST

C15

 

 

 

 

 

 

 

H15

VSS

N15

VCC

 

 

 

XINT4

 

B3

 

 

 

DP1

C16

 

 

 

 

 

 

 

H16

VCC

N16

A16

 

 

 

 

XINT6

 

B4

 

 

 

DP3

C17

 

 

 

 

 

 

 

H17

A9

N17

A15

 

 

 

 

XINT7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B5

 

 

 

TCK

D1

 

 

 

D5

J1

D12

P1

D19

 

 

 

 

 

 

 

 

 

 

 

 

 

B6

 

 

TMS

D2

 

 

 

D2

J2

VCC

P2

D20

B7

 

 

 

VCC

D3

 

 

 

NC

J3

VSS

P3

D22

B8

 

 

 

 

 

 

 

 

 

 

D15

 

 

 

 

 

 

 

J15

VSS

P15

A20

 

 

PCHK

 

 

 

 

NMI

 

B9

 

 

 

VCC

D16

 

 

 

A2

J16

VCC

P16

A19

B10

VCCPLL

D17

 

 

 

A3

J17

A10

P17

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B11

 

 

 

VCC

E1

 

 

 

D7

K1

D13

Q1

D21

B12

 

 

 

VCC

E2

 

 

 

D4

K2

VCC

Q2

D23

B13

 

 

 

NC

E3

 

 

 

D0

K3

VSS

Q3

D26

24

Datasheet

Image 24
Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables Date History80960Hx AC Characteristics on Date Revision HistoryThis page intentionally left blank Hx Product Description Product Core Voltage Operating Frequency bus/coreKey 80960Hx Features I960 Processor FamilyOn-Chip Caches and Data RAM Bit When Set Fail Codes For Bist bit 7 =Remaining Fail Codes bit 7 = Comparison Branch Call/Return Fault Instruction Set SummaryHx Instruction Set Data Movement Arithmetic Logical Bit / Bit Field / ByteHA/HD/HT Package Types and Speeds Package/Name Device Core Speed Bus Speed Order # MHzSymbol Description Pin DescriptionsPin Description Nomenclature Hx Processor Family Pin Descriptions Sheet 1 Name Type DescriptionHx Processor Family Pin Descriptions Sheet 2 SUPHx Processor Family Pin Descriptions Sheet 3 HoldHx Processor Family Pin Descriptions Sheet 4 ClkinHx 168-Pin PGA Pinout- View from Top Pins Facing Down 80960Hx Mechanical DataHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1 Signal NamePin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Package Thermal Specifications Equation 1. Calculation of Ambient Temperature TAHx 168-Pin PGA Package Thermal Characteristics Maximum TA at Various Airflows in C PGA Package OnlyAirflow-ft/min m/sec 600Hx 208-Pin PQ4 Package Thermal Characteristics Maximum TA at Various Airflows in C PQ4 Package OnlyThermal Resistance C/Watt Airflow ft./min m/sec Parameter 400PowerQuad4 Plastic Package Heat Sink AdhesivesStepping Register Information Fields of 80960Hx Device ID Hx Device ID Model TypesDevice ID Version Numbers for Different Steppings Sources for Accessories SocketsAbsolute Maximum Ratings Operating ConditionsAbsolute Maximum Ratings Operating ConditionsRecommended Connections VCC5 Pin Requirements VdiffVccpll Pin Requirements Sym Parameter Min Max UnitsD.C.Specifications Hx D.C. Characteristics Sheet 1Symbol Parameter Min Typ Max Units Hx D.C. Characteristics Sheet 2A.C. Specifications Hx A.C. Characteristics Sheet 1Symbol Parameter Min Max Units Input Clock 1 Synchronous Outputs 1, 2, 3Hx A.C. Characteristics Sheet 2 Relative Output Timings 1, 2, 3, 6Relative Input Timings 1, 7 C. Characteristics Notes Hx Boundary Scan Test Signal Timings1 A.C. Test Conditions A.C. Timing Waveforms Clkin WaveformOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Once Mode Reset OnceNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States 80960Hx Boundary Scan Chain Hx Boundary Scan Chain Sheet 1Boundary Scan Cell Cell Type Comment Hx Boundary Scan Chain Sheet 2 LockbarHx Boundary Scan Chain Sheet 3 NmibarHx Boundary Scan Chain Sheet 4 PchkBoundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.