Intel 80960HT, 80960HD, 80960HA manual Hx Processor Family Pin Descriptions Sheet 4, Clkin

Page 19

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)

 

 

Name

Type

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is

 

 

 

 

 

 

 

 

 

 

 

 

synchronized to CLKIN. All input and output timings are specified relative to

 

 

CLKIN

I

 

CLKIN.

 

 

 

For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying

 

 

 

 

 

 

 

 

 

 

 

 

the CLKIN frequency by three.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

RESET forces the device into reset.

RESET

causes all external and internal

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

signals to return to their reset state (when defined). The rising edge of RESET

 

 

A(L)

 

 

 

 

 

 

 

 

 

 

 

 

starts the processor boot sequence.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

SELF TEST, when asserted during the rising edge of

 

causes the

 

 

STEST

RESET,

 

 

S(L)

 

processor to execute its built in self-test.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

FAIL indicates a failure of the processor’s built-in self-test performed during

 

 

 

 

 

 

 

 

 

 

 

initialization. FAIL is asserted immediately out of reset and toggles during self-test

 

 

 

 

 

 

 

 

 

 

H(Q)

 

 

 

 

 

 

FAIL

 

to indicate the status of individual tests. When self-test passes, FAIL is de-

 

 

 

 

 

B(Q)

 

 

 

 

 

 

 

 

 

 

 

 

asserted and the processor branches to the user’s initialization code. When self-

 

 

 

 

 

 

 

 

 

 

R(0)

 

 

 

 

 

 

 

 

 

 

 

 

test fails, the FAIL pin asserts and the processor ceases execution.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ON-CIRCUIT EMULATION control: the processor samples this pin during reset.

 

 

 

 

 

 

 

 

 

 

I

 

When it is asserted low at the end of reset, the processor enters ONCE mode. In

 

 

 

ONCE

 

ONCE mode, the processor stops all clocks and floats all output pins except the

 

 

 

 

 

 

 

 

 

 

 

 

TDO pin. ONCE uses an internal pull-up resistor; see RPU definition in Table 22,

 

 

 

 

 

 

 

 

 

 

 

 

“80960Hx DC Characteristics” on page 40. Pull this pin high when not in use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

I

 

TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan

 

 

 

 

 

 

testing.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

I

 

TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing.

 

 

 

 

 

 

TDI uses an internal pull-up resistor; see RPU definition in Table 22, “80960Hx DC

 

 

 

 

 

 

 

 

 

 

 

 

Characteristics” on page 40.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

O

 

TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan

 

 

 

 

 

 

testing. ONCE does not disable this pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST RESET asynchronously resets the Test Access Port (TAP) controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRST

 

 

 

 

 

 

 

 

 

 

I

 

must be held low at least 10,000 clock cycles after power-up. One method is to

 

 

 

 

TRST

 

provide TRST with a separate power-on-reset circuit. TRST includes an internal

 

 

 

 

 

 

 

 

 

 

 

 

pull-up resistor; see RPU definition in Table 22, “80960Hx DC Characteristics” on

 

 

 

 

 

 

 

 

 

 

 

 

page 40. Pull this pin low when not in use.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the

 

 

 

 

 

TMS

I

 

sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan

 

 

 

 

 

 

testing. TMS uses an internal pull-up resistor; see RPU definition in Table 22,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“80960Hx DC Characteristics” on page 40.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC5

I

 

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O

 

 

 

 

buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When

 

 

 

 

 

 

 

 

 

 

 

 

all inputs are from 3.3 V components, connect this signal to 3.3 V.

 

 

 

 

 

 

VCCPLL

I

 

PLL VOLTAGE is the +3.3 VDC analog input for the PLL.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOLTAGE DETECT signal allows external system logic to distinguish between a

 

 

 

 

 

 

 

 

 

 

 

 

5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active

 

VOLDET

O

 

low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is

 

 

available only on the PGA version.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = 80960Hx

 

 

 

 

 

 

 

 

 

 

 

 

1 = 80960Cx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Datasheet

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Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables History DateDate Revision History 80960Hx AC Characteristics onThis page intentionally left blank Product Core Voltage Operating Frequency bus/core Hx Product DescriptionI960 Processor Family Key 80960Hx FeaturesOn-Chip Caches and Data RAM Fail Codes For Bist bit 7 = Bit When SetRemaining Fail Codes bit 7 = Data Movement Arithmetic Logical Bit / Bit Field / Byte Comparison Branch Call/Return FaultInstruction Set Summary Hx Instruction SetPackage/Name Device Core Speed Bus Speed Order # MHz HA/HD/HT Package Types and SpeedsPin Descriptions Symbol DescriptionPin Description Nomenclature Name Type Description Hx Processor Family Pin Descriptions Sheet 1SUP Hx Processor Family Pin Descriptions Sheet 2Hold Hx Processor Family Pin Descriptions Sheet 3Clkin Hx Processor Family Pin Descriptions Sheet 480960Hx Mechanical Data Hx 168-Pin PGA Pinout- View from Top Pins Facing DownHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Signal Name Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1Pin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Equation 1. Calculation of Ambient Temperature TA Package Thermal Specifications600 Hx 168-Pin PGA Package Thermal CharacteristicsMaximum TA at Various Airflows in C PGA Package Only Airflow-ft/min m/sec400 Hx 208-Pin PQ4 Package Thermal CharacteristicsMaximum TA at Various Airflows in C PQ4 Package Only Thermal Resistance C/Watt Airflow ft./min m/sec ParameterHeat Sink Adhesives PowerQuad4 Plastic PackageStepping Register Information Hx Device ID Model Types Fields of 80960Hx Device IDDevice ID Version Numbers for Different Steppings Sockets Sources for AccessoriesOperating Conditions Absolute Maximum RatingsOperating Conditions Absolute Maximum RatingsVCC5 Pin Requirements Vdiff Recommended ConnectionsSym Parameter Min Max Units Vccpll Pin RequirementsHx D.C. Characteristics Sheet 1 D.C.SpecificationsSymbol Parameter Min Typ Max Units Sheet 2 Hx D.C. CharacteristicsSynchronous Outputs 1, 2, 3 A.C. SpecificationsHx A.C. Characteristics Sheet 1 Symbol Parameter Min Max Units Input Clock 1Relative Output Timings 1, 2, 3, 6 Hx A.C. Characteristics Sheet 2Relative Input Timings 1, 7 Hx Boundary Scan Test Signal Timings C. Characteristics Notes1 A.C. Test Conditions Clkin Waveform A.C. Timing WaveformsOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Reset Once Once ModeNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States Hx Boundary Scan Chain Sheet 1 80960Hx Boundary Scan ChainBoundary Scan Cell Cell Type Comment Lockbar Hx Boundary Scan Chain Sheet 2Nmibar Hx Boundary Scan Chain Sheet 3Pchk Hx Boundary Scan Chain Sheet 4Boundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
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