Intel 80960HD, 80960HT, 80960HA manual Hx Processor Family Pin Descriptions Sheet 3, Hold

Page 18

80960HA/HD/HT

Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)

 

Name

Type

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HOLD REQUEST signals that an external agent requests access to the

 

 

 

 

 

 

 

 

processor’s address, data, and control buses. When HOLD is asserted, the

 

 

 

 

 

 

 

I

processor:

 

 

 

 

HOLD

Completes the current bus request.

 

 

 

 

S(L)

 

 

 

 

 

 

 

 

 

 

Asserts HOLDA and floats the address, data, and control buses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When HOLD is deasserted, the HOLDA pin is deasserted and the processor

 

 

 

 

 

 

 

 

reassumes control of the address, data, and control pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

HOLD ACKNOWLEDGE indicates to an external master that the processor has

 

HOLDA

H(1)

relinquished control of the bus. The processor grants HOLD requests and enters

 

the HOLDA state while the RESET pin is asserted.

 

 

 

 

B(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(Q)

HOLDA is never granted while

LOCK

is asserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS BACKOFF forces the processor to immediately relinquish control of the bus

 

 

 

 

 

 

 

 

on the next clock cycle. When READY/BTERM is enabled and:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

When

BOFF

is asserted, the address, data, and control buses are floated on the

 

BOFF

next clock cycle and the current access is aborted.

 

 

 

 

S(L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When BOFF is deasserted, the processor resumes by regenerating the aborted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bus access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

See Figure 16 on page 48 for

BOFF

timing requirements.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

BUS REQUEST indicates that a bus request is pending in the bus controller.

 

BREQ

H(Q)

BREQ does not indicate whether or not the processor is stalled. See BSTALL for

 

B(Q)

processor stall status. BREQ may be used with BSTALL to indicate to an external

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(0)

bus arbiter the processor’s bus ownership requirements.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

BUS STALL indicates that the processor has stalled pending the result of a

BSTALL

H(Q)

request in the bus controller. When BSTALL is asserted, the processor must

B(Q)

regain bus ownership to continue processing (i.e., it may no longer execute

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R(0)

strictly out of on-chip cache memory).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYCLE TYPE indicates the type of bus cycle currently being started or processor

 

 

 

 

 

 

 

 

state. CT3:0 encoding follows:

 

 

 

 

 

 

 

 

 

 

 

Cycle Type

ADSCT3:0

 

 

 

 

 

 

 

O

Program-initiated access using 8-bit bus

00000

 

 

 

 

 

 

 

 

 

Program-initiated access using 16-bit bus

00001

 

 

 

 

 

 

 

 

 

H(Z)

 

 

 

CT3:0

Program-initiated access using 32-bit bus

00010

 

 

 

 

 

 

 

 

 

B(Z)

Event-initiated access using 8-bit bus

00100

 

 

 

 

 

 

 

 

 

R(Z)

Event-initiated access using 16-bit bus

00101

 

 

 

 

 

 

 

 

 

 

Event-initiated access using 32-bit bus

00110

 

 

 

 

 

 

 

 

 

 

Reserved

00X11

 

 

 

 

 

 

 

 

Reserved for future products

01XXX

 

 

 

 

 

 

 

 

Reserved

1XXXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL INTERRUPT pins are used to request interrupt service. These pins

 

 

 

 

 

 

 

 

may be configured in three modes:

 

 

 

 

 

 

 

 

 

 

 

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated

 

 

 

 

 

 

 

I

inputs may be programmed to be level (low or high) or edge (rising or falling)

 

 

 

 

 

 

 

sensitive.

 

 

 

XINT7:0

A(E)

 

 

 

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt

 

 

 

 

 

 

 

A(L)

 

 

 

 

 

 

 

pins are level sensitive in this mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pins

 

 

 

 

 

 

 

 

Mixed Mode: The

XINT7:5

pins act as dedicated sources and the

XINT4:0

 

 

 

 

 

 

 

 

act as the five most significant bits of a vectored source. The least significant bits

 

 

 

 

 

 

 

 

of the vectored source are set to “010” internally.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

 

 

NMI

 

 

A(E)

NMI is the highest priority interrupt source. NMI is falling edge triggered.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

Datasheet

Page 17 Page 19
Image 18
Page 17 Page 19
Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables Date History80960Hx AC Characteristics on Date Revision HistoryThis page intentionally left blank Hx Product Description Product Core Voltage Operating Frequency bus/coreKey 80960Hx Features I960 Processor FamilyOn-Chip Caches and Data RAM Bit When Set Fail Codes For Bist bit 7 =Remaining Fail Codes bit 7 = Hx Instruction Set Comparison Branch Call/Return FaultInstruction Set Summary Data Movement Arithmetic Logical Bit / Bit Field / ByteHA/HD/HT Package Types and Speeds Package/Name Device Core Speed Bus Speed Order # MHzSymbol Description Pin DescriptionsPin Description Nomenclature Hx Processor Family Pin Descriptions Sheet 1 Name Type DescriptionHx Processor Family Pin Descriptions Sheet 2 SUPHx Processor Family Pin Descriptions Sheet 3 HoldHx Processor Family Pin Descriptions Sheet 4 ClkinHx 168-Pin PGA Pinout- View from Top Pins Facing Down 80960Hx Mechanical DataHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1 Signal NamePin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Package Thermal Specifications Equation 1. Calculation of Ambient Temperature TAAirflow-ft/min m/sec Hx 168-Pin PGA Package Thermal CharacteristicsMaximum TA at Various Airflows in C PGA Package Only 600Thermal Resistance C/Watt Airflow ft./min m/sec Parameter Hx 208-Pin PQ4 Package Thermal CharacteristicsMaximum TA at Various Airflows in C PQ4 Package Only 400PowerQuad4 Plastic Package Heat Sink AdhesivesStepping Register Information Fields of 80960Hx Device ID Hx Device ID Model TypesDevice ID Version Numbers for Different Steppings Sources for Accessories SocketsAbsolute Maximum Ratings Absolute Maximum RatingsOperating Conditions Operating ConditionsRecommended Connections VCC5 Pin Requirements VdiffVccpll Pin Requirements Sym Parameter Min Max UnitsD.C.Specifications Hx D.C. Characteristics Sheet 1Symbol Parameter Min Typ Max Units Hx D.C. Characteristics Sheet 2Symbol Parameter Min Max Units Input Clock 1 A.C. SpecificationsHx A.C. Characteristics Sheet 1 Synchronous Outputs 1, 2, 3Hx A.C. Characteristics Sheet 2 Relative Output Timings 1, 2, 3, 6Relative Input Timings 1, 7 C. Characteristics Notes Hx Boundary Scan Test Signal Timings1 A.C. Test Conditions A.C. Timing Waveforms Clkin WaveformOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Once Mode Reset OnceNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States 80960Hx Boundary Scan Chain Hx Boundary Scan Chain Sheet 1Boundary Scan Cell Cell Type Comment Hx Boundary Scan Chain Sheet 2 LockbarHx Boundary Scan Chain Sheet 3 NmibarHx Boundary Scan Chain Sheet 4 PchkBoundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
Top Page Image Contents