Intel 80960HA, 80960HD, 80960HT manual Burst, Pipelined Read Request with Wait States, 16-Bit Bus

Page 71

80960HA/HD/HT

Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus

PMCON

External

 

Pipe-

 

Bus

 

 

Parity

 

 

 

 

 

 

Function

 

 

Odd

 

 

 

 

 

 

NRAD

Ready

Burst

 

 

NXDA

 

NWDD

NWAD

NRDD

Lining

 

Width

Parity

 

Enable

 

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

29

28

24

 

23-22

21

 

20

19-16

 

15-14

12-8

7-6

4-0

Value

X

Enabled

ON

 

16-Bit

X

 

Enabled

X

 

X

X

1

2

x

1

1

 

01

x

 

1

xxxx

 

xx

xxxxx

01

00010

 

NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

A’

 

 

2

 

 

A

2

1

D

1

D

1

D

1

D

2

1

D’

CLKIN

 

 

 

 

 

 

 

 

 

 

 

 

 

ADS

 

 

 

 

 

 

 

 

 

 

 

 

 

A31:4, SUP,

 

 

 

 

 

 

 

 

 

 

 

 

 

CT3:0, D/C,

 

 

 

 

Valid

 

 

 

 

 

Valid

 

In-

BE0/BLC,

 

 

 

 

 

 

 

 

 

 

valid

 

 

 

 

 

 

 

 

 

 

 

 

BE3/BHE,

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK

 

 

 

 

 

 

 

 

 

 

 

 

In-

W/R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3:2

 

A3:2 = 00 or 10

 

 

A3:2 = 01 or 11

 

Valid

 

In-

 

 

 

 

 

valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE1/A1

 

 

 

 

 

 

 

 

 

 

Valid

 

In-

 

 

 

 

 

 

 

 

 

 

 

valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D31:0,

 

 

 

D15:0

 

D15:0

D15:0

 

D15:0

 

D15:0

 

 

 

A1=0

 

 

A1=1

A1=0

 

A1=1

 

D’

DP3:0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WAIT

 

 

 

 

 

 

 

 

 

 

 

 

 

BLAST

 

 

 

 

 

 

 

 

 

 

 

 

 

DT/R

 

 

 

 

 

 

 

 

 

 

 

 

 

DEN

 

 

 

 

 

 

 

 

 

 

 

 

 

PCHK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. Non-pipelined request concludes, pipelined reads begin

 

 

 

 

 

 

2. Pipelined reads conclude, non-pipelined requests begin

 

 

 

 

 

Datasheet

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Contents 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Contents Contents Tables History DateDate Revision History 80960Hx AC Characteristics onThis page intentionally left blank Product Core Voltage Operating Frequency bus/core Hx Product DescriptionI960 Processor Family Key 80960Hx FeaturesOn-Chip Caches and Data RAM Remaining Fail Codes bit 7 = Bit When SetFail Codes For Bist bit 7 = Data Movement Arithmetic Logical Bit / Bit Field / Byte Comparison Branch Call/Return FaultInstruction Set Summary Hx Instruction SetPackage/Name Device Core Speed Bus Speed Order # MHz HA/HD/HT Package Types and SpeedsPin Description Nomenclature Symbol DescriptionPin Descriptions Name Type Description Hx Processor Family Pin Descriptions Sheet 1SUP Hx Processor Family Pin Descriptions Sheet 2Hold Hx Processor Family Pin Descriptions Sheet 3Clkin Hx Processor Family Pin Descriptions Sheet 480960Hx Mechanical Data Hx 168-Pin PGA Pinout- View from Top Pins Facing DownHx 168-Pin PGA Pinout- View from Bottom Pins Facing Up Pin Hx 168-Pin PGA Pinout- Signal Name Order Sheet 1Signal Name Hx 168-Pin PGA Pinout- Signal Name Order Sheet 2 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 1 Hx 168-Pin PGA Pinout- Pin Number Order Sheet 2 I960 Hx PQ4 Pinout- Signal Name Order Sheet 1 Hx PQ4 Pinout- Signal Name Order Sheet 2 Pin Number Order Sheet 1 Pin Number Order Sheet 2 Equation 1. Calculation of Ambient Temperature TA Package Thermal Specifications600 Hx 168-Pin PGA Package Thermal CharacteristicsMaximum TA at Various Airflows in C PGA Package Only Airflow-ft/min m/sec400 Hx 208-Pin PQ4 Package Thermal CharacteristicsMaximum TA at Various Airflows in C PQ4 Package Only Thermal Resistance C/Watt Airflow ft./min m/sec ParameterStepping Register Information PowerQuad4 Plastic PackageHeat Sink Adhesives Device ID Version Numbers for Different Steppings Fields of 80960Hx Device IDHx Device ID Model Types Sockets Sources for AccessoriesOperating Conditions Absolute Maximum RatingsOperating Conditions Absolute Maximum RatingsVCC5 Pin Requirements Vdiff Recommended ConnectionsSym Parameter Min Max Units Vccpll Pin RequirementsSymbol Parameter Min Typ Max Units D.C.SpecificationsHx D.C. Characteristics Sheet 1 Sheet 2 Hx D.C. CharacteristicsSynchronous Outputs 1, 2, 3 A.C. SpecificationsHx A.C. Characteristics Sheet 1 Symbol Parameter Min Max Units Input Clock 1Relative Input Timings 1, 7 Hx A.C. Characteristics Sheet 2Relative Output Timings 1, 2, 3, 6 Hx Boundary Scan Test Signal Timings C. Characteristics Notes1 A.C. Test Conditions Clkin Waveform A.C. Timing WaveformsOutput Float Waveform Hold Acknowledge Timings TCK Waveform Output Delay and Output Float for TBSOV1 and TBSOF1 Rise and Fall Time Derating at 85 C and Minimum VCC ICC Active Thermal vs. Frequency Output Delay vs. Temperature Bus ∼ ∼ Reset Once Once ModeNon-Burst, Non-Pipelined Requests without Wait States Non-Burst, Non-Pipelined Read Request with Wait States Non-Burst, Non-Pipelined Write Request with Wait States BE30, Lock Blast DT/R DEN A314, SUP CT30, D/C Valid Lock Blast DT/R DEN A314, SUP Valid CT30, D/C Lock Blast DT/R DEN Wait Blast DT/R DEN Pchk Wait Blast BE30, Lock Burst, Pipelined Read Request with Wait States, 32-Bit Bus Burst, Pipelined Read Request with Wait States, 8-Bit Bus Burst, Pipelined Read Request with Wait States, 16-Bit Bus Using External Ready Terminating a Burst with Bterm Breq and Bstall Operation Clkin ADS Blast Ready Hold Functional Timing Lock Delays Holda Timing Byte Offset Word Offset 80960HA/HD/HT Summary of Aligned and Unaligned Transfers for 16-Bit Bus Summary of Aligned and Unaligned Transfers for 8-Bit Bus Idle Bus Operation Bus States Boundary Scan Cell Cell Type Comment 80960Hx Boundary Scan ChainHx Boundary Scan Chain Sheet 1 Lockbar Hx Boundary Scan Chain Sheet 2Nmibar Hx Boundary Scan Chain Sheet 3Pchk Hx Boundary Scan Chain Sheet 4Boundary Scan Description Language Example Adsbar Supbar E03, C02, D02, C01, E02, D01, F02, E01, F01 Bypass Input BC1 BEBAR3 XINTBAR7 80960HA/HD/HT Adsbar Adsbar Bebar Oncebar Pchkbar 100 Datasheet 101 102 Datasheet 103 104

80960HT, 80960HA, 80960HD specifications

The Intel 80960 family of microprocessors, introduced in the late 1980s, marked a significant evolution in the landscape of embedded systems and high-performance computing. The series included notable members such as the 80960HD, 80960HA, and 80960HT, each offering distinct features, technologies, and characteristics tailored for specific applications.

The Intel 80960HD was primarily designed for high-performance applications, such as real-time processing and advanced embedded control systems. With a robust architecture, the 80960HD featured a 32-bit data bus and a 32-bit address bus, enabling it to access a larger memory space and providing superior performance for computational tasks. It included a sophisticated instruction set that facilitated efficient execution, particularly for computationally intensive tasks. The internal architecture also supported pipelining, allowing multiple instructions to be processed simultaneously, thus enhancing throughput.

The 80960HA variant was tailored for high-availability applications, making it ideal for embedded systems where reliability is paramount. This model incorporated features that emphasized fault tolerance and stability, ensuring that systems relying on it could maintain operational integrity even in the event of component failures. The 80960HA showcased enhanced error detection and correction capabilities, which contributed to its reputation as a dependable choice for mission-critical applications.

On the other hand, the 80960HT was designed to meet the needs of high-performance telecommunications and networking applications. Recognized for its ability to handle multiple tasks concurrently, the 80960HT included advanced features such as built-in support for multitasking and real-time processing. This made it an excellent fit for applications that demanded rapid data handling and processing, such as routers and switches in networking environments. Its architecture allowed for efficient context switching, ensuring that multiple processes could execute seamlessly.

All three variants utilized the same family architecture, enabling easy integration and compatibility across different applications. They also supported various memory management techniques, such as virtual memory and caching, enhancing their performance in diverse operating conditions. With their combination of high processing power, reliability, and flexibility, the Intel 80960 family of microprocessors played a crucial role in advancing embedded computing technologies, paving the way for modern-day processors and systems. The 80960 series remains a noteworthy chapter in the evolution of microprocessor design, reflecting the growing demands of the computing landscape during its time.
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