Quatech RS-422 user manual External Connections, Jumper/Channel correspondence

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7 External Connections

The DSCLP-200/300 provides four differential communication signals per channel. The two output signals are Transmit Data (TxD) and Auxiliary Output (AUXOUT). The two input signals are Receive Data (RxD) and Auxiliary Input (AUXIN). A ground signal is also provided.

The available input signals for AUXIN are Clear To Send (CTS) and the Receive Clock (RCLK). The available output signals for AUXOUT are Request To Send (RTS), the Transmit Clock (XCLK), and the AUXIN signal (for loopback). Either half-duplex or full-duplex operation can be selected for each communications channel. If half-duplex operation is selected, one of the UART's signals (either DTR or RTS) is used to enable the transmitter drivers. The inverse of the transmitter enable can be used to enable the receiver drivers.

Factory-installed resistors allow for signal line termination in compliance with the RS-422 and RS-485 standards. The desired termination can be selected or removed per port by applying a jumper.

Configuration is done using jumpers J1 through J4 for termination selection, and jumpers J5 through J8 for interface signal routing. Each jumper block provides the same functions for its particular channel.

Channel

Termination

Signal routing

 

 

 

Port 1

J1, J2

J5, J6

 

 

 

Port 2

J3, J4

J7, J8

 

 

 

Figure 17 --- Jumper/Channel correspondence

XCLK

6

3

RCLK

Jumpers J5, J7

 

5

2

AUXIN

AUXOUT

 

RTS

4

1

CTS

 

Tx ENABLE

6

3

Rx ENABLE

Jumpers J6, J8

 

 

 

 

Tx ENABLE

5

2

RTS

 

Tx ENABLE

4

1

DTR

Half-duplex

if 3-6 shorted

Figure 18 --- Pinout of jumpers J5-J8

DSCLP-200/300 User's Manual

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Contents DSCLP-200/300 Page Serial Number Declaration of Conformity Table of Contents General Information Hardware Configuration RS-422 or RS-485 Signal Line TerminationSignal Connections Full-duplex/Half-duplex Operation1 CTS0SEL, CTS1SEL J10,17 2 AUX0SEL1,0, AUX1SEL1,0 J12,11,19,18RCLK0SEL, RCLK1SEL J13 RXEN0SEL, RXEN1SEL J16 Enable Scratchpad Register SPAD, J24 TGL0SEL1,0, TGL1SEL1,0 J15,14,22,21 Clock Rate and Optional RegistersEnable scratchpad registers Force High-Speed Uart Clock X2 or X4, J4-J5X4 mode Hardware Installation Jumper/connector locationsAddress Map and Special Registers Base Address and Interrupt Level IRQEnabling the Special Registers Interrupt Status RegisterQuatech Modem Control Register Quatech Modem Control RegisterOptions Register Enhanced Serial Adapter IdentificationClock Rate Multiplier RR1 RR0Windows Configurations Windows MillenniumWindows Windows Windows Using the New Hardware Found Wizard Viewing Resources with Device Manager Page Page Page OS/2 Other Operating SystemsWindows NT DOS and other operating systemsQTPCI.EXE Basic Mode display QTPCI.EXE Expert Mode display External Connections Jumper/Channel correspondenceRTS/CTS Handshake RclkXclk AUXIN/AUXOUT LoopbackHalf-Duplex/Full-Duplex Selection Half- or full-duplex selection Termination Resistors RS-422/485 Line termination resistance valuesDSCLP-200/300 connector definitions RS-422/485 Peripheral ConnectionPCI Resource Map INTA#Specifications With 64-byte FIFOs optionalTroubleshooting Computer will not boot upDSCLP-200/300 Revision December