CH Tech EM405D user manual Specifications, Maximum Ratings

1.2.2 Specifications

MAXIMUM RATINGS

Parameter	Condition	Rating	Units
Operating Temperature		0 to +60	°C
Non-Operating Temperature		-40 to +75	°C
Humidity	non-condensing	5 to 95	%
Input DC Power Level		12.6	V max.
Power Consumption	Support for two M-modules at full power	30	Watts
External Trigger Input	Power Off	± 40	V
	Power On	± 36	V

CHARACTERISTICS

			Limit
Parameter	Conditions	Min	Typ.	Max	Units
Data Transfers
Throughput	Wired Ethernet – block read 1, 3			90K	bytes/sec
	Wired Ethernet – block write 2, 3			40K	bytes/sec
	Wireless Ethernet – block read 1, 3			23K	bytes/sec
	Wireless Ethernet – block write 2, 3			14K	bytes/sec
Input Power Supply
Level	DC	11.4	12.0	12.6	V
Current	for full M-module support	2.5			A
Ripple/noise	20MHz bandwidth	-1.5		+1.5	%
Power Consumption
Carrier	-0001 wired Ethernet	460	470	550	mA
	-0002 wireless Ethernet	500	510	590	mA
M-modules (each position)	+5V			1.0	A
	+12V			200	mA
	-12V			200	mA
Triggers
Output Level	into a high impedance load	3.8	5.0	5.4	V
Output Impedance			50		Ω
Input Level	TLVL = 0 4		2.5		V
	TLVL = 1		1.4		V
Input Impedance	TIMP = 0 4	100K			Ω
	TIMP = 1		50		Ω
External Trigger Delay	External connector to M-module		30	40	ns
	M-module to external connector		30	40	ns
	M-module to M-module		30	40	ns
Cooling
Temperature Rise				20	°C
Temperature Accuracy		-2		+2	°C

Notes:

1.12-24ms latency occurs on each command issued. The effect of this latency is reduced by transferring large amounts of data with a single block read command. Maximum read throughput is achieved by reading >64K bytes of data from a FIFO type register on an M-module using the Block Read command. Host software may vary and can limit the maximum throughput.

2.The maximum number of bytes that can be written in a single block write command is 1024.

3.Ethernet is a non-deterministic communications interface. Realized throughput may be significantly degraded by network activity or other factors that may affect network performance.

4.TLVL and TIMP refer to register bits in the Reset & Trigger Control register. Refer to section 4.3.5.

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