Compaq M-LVDS manual Board Layout, 1. Assembly Drawing

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Board Layout

3.2 Board Layout

Figure 3−1. Assembly Drawing

J8

J7

J18

J17

J14

J13

J2

J1

R12	GND01	VCC01	W10GND	VCC	R1
TP4W4 W3	TP3	GND01	GND		W2 W1TP1

	VCC01	VCC01	VCC	TP2	VCC
J15						J11
	GND01		W8		GND

				R3
VCC01		R13	MADE	VCC
	R14		IN	R2
	R14	U2	IN	TEXAS INSTRUMENTS U1
		U2	U.S.A.	TEXAS INSTRUMENTS U1

J16	R15	A/W NO. # 6424409B				R7		R4	J12
	R15	PWA.	EVM.			R7		R4
GND01	P3	SN65MLVD				P2		P1	GND
GND01	R16	SERIAL NO.				R6		R5	GND
	R16					R6		R5
R18	R17			W7		R11		R8
R18	R17
J10	J9		VCC01		J6	J5		J4	J3
J10	J9		VCC01	VCC	J6	J5	R9	J4	J3
			GND01	GND		R10	R9
			GND01	GND
				W9

The top layer of the EVM contains the controlled impedance and matched length traces.

Figure 3−2. Top Layer

Bill of Materials, Board Layout, and PCB Construction

3-3

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Contents User’s Guide Important Notice EVM Important Notice EVM Warnings and Restrictions Preface How to Use This ManualPage Contents Tables FiguresTopic M-LVDS Evaluation Module−1. M-LVDS Devices Supported by the EVM OverviewLvds Standard TIA/EIA−899 Lvds EVM Kit Contents Point-to-Point ConfigurationsMultipoint Multidrop−7. Two-Node Multipoint Circuit EVM Operation With Separate Power SuppliesRecommended Equipment PS1 PS2 PS3Test Setup −1. EVM Configuration Options Typical Cable Test ConfigurationsPoint-to-Point Simplex Transmission Two-Node Multipoint Transmission Point-to-Point Parallel Terminated Simplex Transmission−3. Two-Node Multipoint Transmission −4. Point-to-Point Parallel Simplex Typical Eye Pattern Data Test ResultsDriver Input Receiver #1 Output Receiver #2 Bill of Materials, Board Layout, and PCB Construction −1. M-LVDS EVM Bill of Materials Bill of MaterialsBoard Layout −1. Assembly DrawingÏïïïïïïïïïïïïï Ï Ìììììììììììììì Ì −5. Bottom Layer + 2 Z 374e * 2.9s h PCB ConstructionMicrostripstripline Mils −2. EVM Layer Stack UpThis Appendix contains the EVM schematic SchematicVCC