Sharp MZ-3500 service manual MZ3500 Memory mapper MMR SP6102R-001 signal description, Srdy

MZ3500

2) Memory mapper (MMR) SP6102R-001 signal description

	Polarity
	Signal Name
1	ST	IN	Main CPU DRAM output buffer (LS244) switching strap.
2	DO		Bidirectional main CPU data bus.
		IN/OUT
					(Data bus 0 ~ 7)
9	D7
10	A15		Main CPU address bus.
		IN	Used in the memory mapping logic of the MMR for address output for the DRAM, ROM,and
12	A13		shared RAM.		(Address bus 13 ~ 15)
13	A1	IN	Main CPU address bus.
			Used in the I/O port select logic of the MMR to assign device number.
			Sub-CPU bus request signal.
			•	After power on: Halts the sub-CPU.
14	SRES	OUT	•	After write command (LDA-80H: OUT#FD) by the main CPU- Starts the sub-CPU.
			This signal is issued after transfer of the main CPU program contained in the ROM-IPL.
					(Sub CPU Reset)
			Sub-CPU bus request signal.
			•	After power on: Resets busrequest to sub-CPU.
15	SRQ	OUT	• After write command (LDA-02H1OUT#FC) by the main CPU' Place bus request to the sub-CPU
			This signal is issued to bus of the sub-CPU, after the main CPU writes to the shared RAM a command
			parameter to the sub-CPU or reads the message status from the sub-CPU.
					(Sub CPU Request)
16	AR13		Address signal to the main CPU dynamic RAM.
		OUT	The main CPUaddress signals, A 13-A 15, merged in the memory mapping logic circuit to produce
18	AR15		AR13-AR15. This is means by which the 4 basic and CP/M memory maps are made, along with MS1
			and MSO.
			BASIC interpreter 32KB mask ROM chip select signal.
19	R32	OUT	Valid when SD2 is active (Sharp ROM based BASIC). Command (LDA 02H OUT 3FD)
					(ROM 32K select)
			Internal MMR I/O port select logic signal.
20	IOAB	IN	Goes low by the command IN/OUT #FC-#FF.
					(Input/Output Address)
21	SRDY	IN	Input of ready signal from thesub-CPU.
					(Sub CPU Ready)
			Chip select signal issued from the main CPU to the 8KB mask ROM.
22	ROPB	OUT	Valid with SDOactive (initialize state).
					(ROM ipl)
23	ROAB		Chip select signal for four chip BASIC interpreter 8KB EPROM (A. B. C, D).
		OUT	Valid with SD2 active (Sharp ROM based BASIC).
26	RODS		"R32B (alternate choice with the 32KB mask ROM chip select signal).
					(ROM A~D Buffer)
27	RSAB		Row address select signal for the main CPU dynamic RAM (block A-block D).
~	~	OUT	RAS (ROW ADDRESS SELECT; LINE ADDRESS SELECT) SIGNAL
30	RSDB				(Row address Select)
			Input of bus acknowledge signal from the sub-CPU.
31	SACK	IN	command is written in the shared RAM after acknowledgement from the sub-CPU			1
			At the end of the command cycle bus request is released and the sub CPU executes the command			/

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