Sharp MZ-3500 service manual Vsync, Circuit description

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MZ 3500

4-9. VSYNC

0 40 Digit

From1 80 Digu

(8255 PB7) CH48

80 digit, 16bit/word Master is GDC-2

[Circuit description]

When more than two UPD7220 GDC's are to be operated in parallel, one must be assigned to the master and the other to the slave in order to mantain synchronous display timing. The master and the slave are determined according to the table below. The above circuit shoud be used to compare with the table description.

""~~~-~^GDC-1 (character)

			CH48 = 0 40 digit CH48 = 1 80 digit
	GDC-2 (graphic)"""	^^^
	Without VRAM PWB		GDC1 (character)	GDC 1
	Without VRAM PWB		is the master.	GDC 1
			is the master.
	8-bit structure [0816=0)		GDC1	GDC 1
	(48KB, 200 raster)		GDC1	GDC 1
	(48KB, 200 raster)
	16-bit structure [0816=1]		GDC1	GDC2 (Graphic)
	(4896KB, 400 rasters)		GDC1	GDC2 (Graphic)
	(4896KB, 400 rasters)

The master GDC must be set as indicated above.

[Oprational example]

If it was set to 80 digit, 16 bit/word mode SRES will be

0when CH48 = 1, 0816 = 1 when not in the reset condi- tion. These signals are supplied to terminal A (weight 1), B (weight 2), and G (gate), and set terminal Y3 of the decoder 1C LS139 to "0", so that the YSYNC output of the GDC2 is input to terminal EX SYNC of the GDC2.

SRES (From MMR)

40 digit. 16bu/word

80 digit, 8bit/word Master is GDC

40 digit, Sbit'word Master is GDC 1

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Contents Personal Computer Model Z-350 BACKUP, INIT, COPY, DEBUG, Killall TimerMemory VideoSlot Slot2 Refer to the page TIN Circuit DiagramLSI, 1C Cmosic SFDI/FSymbol PresetSdisp Change DispBase Basic Area RAMSystem UserMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MMAO Bank SelectFfff Operational description SD3 RAM based BasicBank ROMMain Memory Mapper Block diagram Relation between MMR main memoryTable below describes address map Main CPU and I/O portThis paragraph discusses main CPU I/O Main CPU \m 0001MZ3500 Sub CPU and I/O portTo Reset Memory mapper MMRSP6102R-001 Block diagramAddress BUS CoabSrdy MZ3500 Memory mapper MMR SP6102R-001 signal descriptionRAS ROW Address Select Line Address Select Signal Pin No RO2B IN/OUTRO1B 1 1 1 1 0 KI1 Dl Do 17 D6 D5 A7 A6 A5A4A3A2AlAO H E X Uhus 1 OD2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationBlue Dot pitchDot color designated by Graphic dotCH AI +,! AT A r + + G CH ATKA7 Ascii CG #1 FFFVideo RAM Structure of Vram #0000 Structure of character Vram When read/write from GDC#07FFA 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KSetup of GCD master/slave 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzMaster/slave setup by combination O signal switchingGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSH CSP-1 Block Diagram» CK HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description3r00 CSP 2 Block DiagramDSP2 OUT CAS OUTGDC Graphic display controller UPD7220 signal description NK-CLC AD15ILC2AT~BTI CSR-1MAGEStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeCsrw C 49H -COMMAND Code Return when all parameters were sentWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty?Explanation 60HVECTE. Dot address is structured on the screen Following manner Dot display program example-1Kind of line solid line I T E C 23HP4 88H P5 HH Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MZ350C Trigger motor on of the timer 555 Selects FDDPort used in the MFD interface is as follows MFM recording methodMedia detection Controls during read, write, seek, and re- calibrate3500 Precompensate Circuit Control during seek and recalibrationPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ 3DSC Side =Aload \128 76 iy 7 EH 77 / FFHTrack 10 sector Indicates the byte position From the top of directoryB144 6145 B146 B147 39 B148 B149 B150 B151 Ii Patat39 B74 B75 1015Data transmission format General specificationMZS500 Example 7-bits, even parity, 1 stop bitOFF AC controlsStart 8251 AC MZ3500 Data output controlKTS RXEN,UTR , T X E N 3SOO9 6.3 200256 128«--N Wl -»8253 OUT 8253AA3 Printer interfacing circuitDAT DS7Data transfer timing General description of the parallel interfaceOutput I/O port map Read Hold Clock circuit SchematicWrite Hold SET DINLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilS I C 3500GP I/O SFD 1/FDipswa SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFSEC FD2\f Canbe in either state Description of each block Block diagramFunctions +5V Switching regulatorTiming chart Alarm generation circuitKey Specification of keyboard controlAt rrn 2s 2s22 21 Key search timingKey StrobeProtocol Key to sub CPU 132.522.5/-s Keyboard controller basic flow XTAL1 XTAL2 Reset INT Keyboard controller signal descriptionPIN ALE DBO DB7 GNDOn OFF Sub-CPU side ProcedureCRT inter face test Shared RAMAbnormal S C I I 00-FFReady O.H Abnormal test ending1 5 c * O DR O.7 ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart SEEK, Read Error Jump \ Boot Address SystemError Load Iocs SEEK& Read105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U URoB IwCAIO MZ-35OO Parts Guide LI S C R I P T I O N No Parts CodeLED PWB IE--or Ooss-zw Parts Code MZ-3500N T K QcnwS C R I P T I O N ConnectorNO. Parts Code MZ-3500Parts Code A a N a DNEW VH S N 7 4 0 6 NCoos Part S C R I P T I O NMark Rank M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitLSI RAM SOCLA a NO. Parts CodeD e Tin N a a Parts CodeMZ-3500 Sharp Corporation