Sharp MZ-3500 General description of the parallel interface, Output, Data transfer timing

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7-3. General description of the parallel interface

The 8255 is used for the LSI to control the parallel inter- face. The 8255 can be set in the following mode.

/PORT A: MODE 0

IPORTB: MODE 1

C:Output

74.Data transfer timing

BUSY

ACK

( 8255 A

vPC-7J

DATA

STROBE

( M 1 N ) l^s(MIN)

Because it is not possible to directly it uses interrupt for key processing ACK signal is latched by means of

sense the ACK signal as and RS232C input, the the OBF pin function

PRINTER: MZ-1P02, MZ-1P03 CE-

330P, 331P, 332P

*Broken line in the above figure represents timing for the CE-330Pand331P.

'For detail of timing, refer to Manual provided with printer.

7-5. General description of control software

Set the 20 second counter.

STROBE OUT

Set the 20 second counter.

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Contents Personal Computer Model Z-350 Timer BACKUP, INIT, COPY, DEBUG, KillallMemory VideoRefer to the page TIN Circuit Diagram Slot Slot2LSI, 1C Cmosic SFDI/FPreset SymbolSdisp Change DispBasic Area RAM BaseSystem UserMZ-1D07 MZ3500 System configuration of Model Software Memory Configuration MS1 = D MSO = 0 LTiming of Reset Signal SD1 System Loading & CP/M ROM-IPLBank Select FfffMAO SD3 RAM based Basic Operational descriptionBank ROMBlock diagram Relation between MMR main memory Main Memory MapperMain CPU and I/O port This paragraph discusses main CPU I/OTable below describes address map 0001 Main CPU \mMZ3500 Sub CPU and I/O portMemory mapper MMRSP6102R-001 Block diagram To ResetAddress BUS CoabMZ3500 Memory mapper MMR SP6102R-001 signal description RAS ROW Address Select Line Address Select SignalSrdy Pin No IN/OUT RO1BRO2B A7 A6 A5A4A3A2AlAO H E X Uhus 1 O 1 1 1 1 0 KI1 Dl Do 17 D6 D5D2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit Specification CRTSummary of video display specification AsciDot pitch BlueDot color designated by Graphic dotCH AT KA7CH AI +,! AT A r + + G #1 FFF Ascii CGVideo RAM Structure of Vram Structure of character Vram When read/write from GDC #07FFA#0000 Read/write by Z-80 via the GDC 640 x 200 dots display mode 8bit16K FV = 60 Hz640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 Hz Setup of GCD master/slaveMaster/slave setup by combination O signal switchingCrtc block diagram Graphic V-RAM AddressPage Master slice LSI CSP-1 SP6102C 002 signal description CSP-1 Block Diagram » CKCSH LSI CSP-2 SP6012C-003 Signal Description HSY2 2BLK2CSP 2 Block Diagram 3r00DSP2 OUT CAS OUTGDC Graphic display controller UPD7220 signal description AD15ILC2 NK-CLCAT~BTI CSR-1MAGECG Address Select Circuit StructureVsync Circuit descriptionCharacter Vram select circuit BlscSet GDC command code Read/write from the Z-80 to V-RAMReturn when all parameters were sent Csrw C 49H -COMMAND CodeWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty?60H ExplanationVECTE. Dot address is structured on the screen Following manner Dot display program example-1I T E C 23H P4 88H P5 HHKind of line solid line Floppy disk OutlineTJ ILJ n VnVn n nV nnn7 Ci D ci IciData MZ3500 MFD interface block diagram FDC UPD765 22 «- o WindowUPD765 signal description Trigger motor on of the timer 555 Selects FDD MZ350CPort used in the MFD interface is as follows MFM recording methodControls during read, write, seek, and re- calibrate Media detection3500 Precompensate Circuit Control during seek and recalibrationVFO circuit Purpose String of data Pulses from the FDD Data windowVFO circuit configuration Filter Phase Detector Amplifier WindowMFM Mode BQAFM mode timing chart \\\\ Side = Aload3DSC 76 iy 7 EH 77 / FFH \128Track 10 sector Indicates the byte position From the top of directoryIi Patat B144 6145 B146 B147 39 B148 B149 B150 B15139 B74 B75 1015General specification Data transmission formatMZS500 Example 7-bits, even parity, 1 stop bitAC controls StartOFF MZ3500 Data output control KTS8251 AC 3SOO RXEN,UTR , T X E N200 9 6.3256 128Wl -» «--N8253 8253 OUTPrinter interfacing circuit AA3DAT DS7General description of the parallel interface OutputData transfer timing I/O port map Clock circuit Schematic Read HoldWrite Hold SET DINMZ3500 PD1990AC Block diagram LSB MSBMmmil » GETE1 J3500 S I CGP I/O SFD 1/FSW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFF DipswaSEC FD2\f Canbe in either state Block diagram FunctionsDescription of each block Switching regulator +5VAlarm generation circuit Timing chartSpecification of keyboard control At rrnKey Key search timing 2s 2s22 21Key Strobe132.5 22.5/-sProtocol Key to sub CPU Keyboard controller basic flow Keyboard controller signal description XTAL1 XTAL2 Reset INTPIN ALE DBO DB7 GNDOn OFF Procedure Sub-CPU sideShared RAM CRT inter face testAbnormal S C I I 00-FFAbnormal test ending 1 5 c * O DR O.7Ready O.H ROM-IPL Main CPU Checker Flow Chart 1/2 Main CPU Checker Flow Chart M? 100101 M7*500Keyboard controller ROM test Keyboard testIPL Flow Chart Jump \ Boot Address System SEEK, Read ErrorError Load Iocs SEEK& ReadSUB CPU IPL Flow Chart 105LJ LJ LJ LJ LJ LJ LJ R R R R F1LU LU U LJ LlJ LJ U U U J l J J L i J L L j l J J L l J L L lIwC AIORoB MZ-35OO Parts Guide LI No Parts Code LED PWBS C R I P T I O N IE--or Ooss-zw MZ-3500 Parts CodeN T K QcnwConnector S C R I P T I O NMZ-3500 NO. Parts CodeParts Code A a N a DVH S N 7 4 0 6 N NEWPart S C R I P T I O N Mark RankCoos J9, MZ1K02,1K03,1K04,1K05 Key unit M2-3500SOC LSI RAMLA a NO. Parts CodeD e Tin Parts Code N a aMZ-3500 Sharp Corporation