Sharp MZ-3500 service manual Keyboard controller ROM test, Keyboard test

Page 95

MZ3500

SUB CPU CHECKER FLOW CHART 2/3

Sei th» timer to 23 hourt.

59minuiei. 58 **corxii

Oc *mb«r 3 III

Printer int M»c* tt»t

SUB CPU CHECKER FLOW CHART 3/3

11-3. Keyboard unit test functions

1)Keyboard controller ROM test

(1)After power on in a normal condition, it starts to carry out the ROMself-test.

If the alpha/symbol (LOCK) LED were to turn on, it indicates a failure in KBC. If not, KBC is satisfactory. t Key self check functional specification (simplified check)

2)Keyboard test

(1)As the power is turned on with the "DEB" in depres- sion, it goes into the keyboard self-test mode.

(2)Depress key in a given sequence. If key is depressed in a correct sequence, it makes the alpha/symbol (LOCK) LED activated each time a key is pushed.

If the key was pushed in a wrong sequence or when a failure is met in the key, it makes the LED blinked.-

(3)It returns to the normal mode upon completion of testing all keys. With this, the LED goes out.

(4)Observe the following key-in sequence to test.

i)Turn the OP/PRO siwtch to the OP side.

ii)Turn on power while pushing the "DEB" key.

iii)Turn the PO/PRO which to the PROside.

iv)Push a key one at a time in accordance with the given sequence.

- 102 -

Image 95

Contents Personal Computer Model Z-350 Video TimerBACKUP, INIT, COPY, DEBUG, Killall MemorySFDI/F Refer to the page TIN Circuit DiagramSlot Slot2 LSI, 1C CmosicChange Disp PresetSymbol SdispUser Basic Area RAMBase SystemMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MMAO Bank SelectFfff ROM SD3 RAM based BasicOperational description BankMain Memory Mapper Block diagram Relation between MMR main memoryTable below describes address map Main CPU and I/O portThis paragraph discusses main CPU I/O Sub CPU and I/O port 0001Main CPU \m MZ3500Coab Memory mapper MMRSP6102R-001 Block diagramTo Reset Address BUSSrdy MZ3500 Memory mapper MMR SP6102R-001 signal descriptionRAS ROW Address Select Line Address Select Signal Pin No RO2B IN/OUTRO1B 1 1 1 1 1 1 FF 14 I N D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 D2 Dl 1 1 1 1 1 0 FE do D4 D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationGraphic dot Dot pitchBlue Dot color designated byCH AI +,! AT A r + + G CH ATKA7 Ascii CG #1 FFFVideo RAM Structure of Vram #0000 Structure of character Vram When read/write from GDC#07FFA 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KO signal switching 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave Master/slave setup by combinationGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSH CSP-1 Block Diagram» CK HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal DescriptionCAS OUT CSP 2 Block Diagram3r00 DSP2 OUTGDC Graphic display controller UPD7220 signal description CSR-1MAGE AD15ILC2NK-CLC AT~BTIStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeFifo Empty? Return when all parameters were sentCsrw C 49H -COMMAND Code Write C 23H Command Code Vecte C 6CH Command CodeFollowing manner Dot display program example-1 60HExplanation VECTE. Dot address is structured on the screenKind of line solid line I T E C 23HP4 88H P5 HH Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MFM recording method Trigger motor on of the timer 555 Selects FDDMZ350C Port used in the MFD interface is as followsControl during seek and recalibration Controls during read, write, seek, and re- calibrateMedia detection 3500 Precompensate CircuitPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ 3DSC Side =Aload Indicates the byte position From the top of directory 76 iy 7 EH 77 / FFH\128 Track 10 sector1015 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 39 B74 B75Example 7-bits, even parity, 1 stop bit General specificationData transmission format MZS500OFF AC controlsStart 8251 AC MZ3500 Data output controlKTS RXEN,UTR , T X E N 3SOO128 2009 6.3 256«--N Wl -»8253 OUT 8253DS7 Printer interfacing circuitAA3 DATData transfer timing General description of the parallel interfaceOutput I/O port map DIN Clock circuit SchematicRead Hold Write Hold SETLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilSFD 1/F 3500S I C GP I/OFD2 SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa SEC\f Canbe in either state Description of each block Block diagramFunctions +5V Switching regulatorTiming chart Alarm generation circuitKey Specification of keyboard controlAt rrn Strobe Key search timing2s 2s22 21 KeyProtocol Key to sub CPU 132.522.5/-s Keyboard controller basic flow ALE DBO DB7 GND Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT PINOn OFF Sub-CPU side ProcedureS C I I 00-FF Shared RAMCRT inter face test AbnormalReady O.H Abnormal test ending1 5 c * O DR O.7 ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart Load Iocs SEEK& Read Jump \ Boot Address SystemSEEK, Read Error Error105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U URoB IwCAIO MZ-35OO Parts Guide LI S C R I P T I O N No Parts CodeLED PWB IE--or Ooss-zw Qcnw MZ-3500Parts Code N T KS C R I P T I O N ConnectorA a N a D MZ-3500NO. Parts Code Parts CodeNEW VH S N 7 4 0 6 NCoos Part S C R I P T I O NMark Rank M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitNO. Parts Code SOCLSI RAM LA aD e Tin N a a Parts CodeMZ-3500 Sharp Corporation