Sharp MZ-3500 service manual UPD765 signal description

Page 53

MZ3500

UPD765 signal description

Pin No.

Signal name

I/O

40

Vcc

-

20

GND

-

19

0

I

1

RESET

1

4

CS

1

13 - 6

DB7 ~ DBO

I/O

3

WR

 

 

 

'

2

RD

1

18

INT

o

5

AO

1

14

DRQ

o

15

DACK

1

29,28

USD, 1

0

26

MFM

o

24

SYNC

o

39

RW/SEEK

o

36

HOLD

0

27

SIDE

0

38

LCT/DIR

0

37

FLTR/STEP

o

35

READY

1

34

WPRT/2 SIDE

1

17

INDEX

'

 

 

33

FLT/TRKO

1

16

TC

1

30

WDATA

0

25

WE

o

21

WCLK

1

Function

+5V

0V

i

Single phase, TTL level clock

Set the FDC into an idle state, and all drive unit interface outputs, except PSO, 1 , and WDATA (don't care), are set to low level In addition, INT and DRW outputs are set to low level DB goes into an input state.

Validates RD and WR signals

Bidirectional, tri-state data bus

Control signal to write data to the FDC via the data bus

Control signal to read data from the FDC via the data bus

The signal used to indicate a service request from the FDC It is issued at every byte in the non- DMA mode, or upon completion execution of a command in the DMA mode

The signal used to select the status register or data register of the FDC for access via the data bus. When 0, it selects the status register When 1. it selects the data register.

FDC to memory data transfer request signal in the DMA mode

The signal that indicates use of the DMA cycle During the DMA cycle, it functions identically toCS.

Drive unit select signal, with which up to four drive units can be selected.

The signal used to designate the operation mode of the VFO circuit When 0, the MFM mode is assigned. When 1, the FM mode is assigned

The signal used to designate the operation mode of the VFO circuit When 1, it permits reading operation. When 0, it prohibits reading operation

Signal used to discriminate the read/write signal from the seek signal that used for drive unit interfacing signal. When 0, it indicates RW When 1 , it indicates

Signal used to load the read/write head

Signal used to select head #0 and head #1 for the double-sided floppy disk drive unit. When 0, it selects head 0. When 1, it selects head 1.

When the RW/seek signal is operating as RW, the signal works as LCT which indicates that the read/write head is selecting the cylinder above 43. When the RW/SEEK is operating as SEEK, it works as DIR which indicate seek direction When 0. seek is made towards outer side When 1, seek is made towards inner side

When the RW/SEEK signal functions as RW, it works as F LTR which resets any fault condition as the seek step signal.

Signal used to indicate that the drive unit is ready for operation

When the RW/SEEK signal is operating as RW, it function as WPRT which indicates that the drive unit or the floppy disk is write protected. When the RW/SEEK is function as the SEEK signal produces 2 SIDE which indicates that a double sided media is in use.

Signal to indicate the physical start point of the track.

When the RW/SEEK signal is operating as RW. it works as FLT which indicates that the drive unit is in a fault condition. When the RW/SEEK is operating as SEEK, it works as TRKO which indicates that the read/write head is on cylinder 0.

Signal used to indicate the termination of a read or write operation

Data written on the floppy disk consists of clock bits and data bits

Signal to indicate write enable to the drive unit

Data write timing signal which is 250kHz in the FM mode or 500kHz in the MFM mode

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Image 53
Contents Personal Computer Model Z-350 BACKUP, INIT, COPY, DEBUG, Killall TimerMemory VideoSlot Slot2 Refer to the page TIN Circuit DiagramLSI, 1C Cmosic SFDI/FSymbol PresetSdisp Change DispBase Basic Area RAMSystem UserMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MMAO Bank SelectFfff Operational description SD3 RAM based BasicBank ROMMain Memory Mapper Block diagram Relation between MMR main memoryTable below describes address map Main CPU and I/O portThis paragraph discusses main CPU I/O Main CPU \m 0001MZ3500 Sub CPU and I/O portTo Reset Memory mapper MMRSP6102R-001 Block diagramAddress BUS CoabSrdy MZ3500 Memory mapper MMR SP6102R-001 signal descriptionRAS ROW Address Select Line Address Select Signal Pin No RO2B IN/OUTRO1B 1 1 1 1 0 KI1 Dl Do 17 D6 D5 A7 A6 A5A4A3A2AlAO H E X Uhus 1 OD2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationBlue Dot pitchDot color designated by Graphic dotCH AI +,! AT A r + + G CH ATKA7 Ascii CG #1 FFFVideo RAM Structure of Vram #0000 Structure of character Vram When read/write from GDC#07FFA 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KSetup of GCD master/slave 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzMaster/slave setup by combination O signal switchingGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSH CSP-1 Block Diagram» CK HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description3r00 CSP 2 Block DiagramDSP2 OUT CAS OUTGDC Graphic display controller UPD7220 signal description NK-CLC AD15ILC2AT~BTI CSR-1MAGEStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeCsrw C 49H -COMMAND Code Return when all parameters were sentWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty?Explanation 60HVECTE. Dot address is structured on the screen Following manner Dot display program example-1Kind of line solid line I T E C 23HP4 88H P5 HH Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MZ350C Trigger motor on of the timer 555 Selects FDDPort used in the MFD interface is as follows MFM recording methodMedia detection Controls during read, write, seek, and re- calibrate3500 Precompensate Circuit Control during seek and recalibrationPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ 3DSC Side =Aload \128 76 iy 7 EH 77 / FFHTrack 10 sector Indicates the byte position From the top of directoryB144 6145 B146 B147 39 B148 B149 B150 B151 Ii Patat39 B74 B75 1015Data transmission format General specificationMZS500 Example 7-bits, even parity, 1 stop bitOFF AC controlsStart 8251 AC MZ3500 Data output controlKTS RXEN,UTR , T X E N 3SOO9 6.3 200256 128«--N Wl -»8253 OUT 8253AA3 Printer interfacing circuitDAT DS7Data transfer timing General description of the parallel interfaceOutput I/O port map Read Hold Clock circuit SchematicWrite Hold SET DINLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilS I C 3500GP I/O SFD 1/FDipswa SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFSEC FD2\f Canbe in either state Description of each block Block diagramFunctions +5V Switching regulatorTiming chart Alarm generation circuitKey Specification of keyboard controlAt rrn 2s 2s22 21 Key search timingKey StrobeProtocol Key to sub CPU 132.522.5/-s Keyboard controller basic flow XTAL1 XTAL2 Reset INT Keyboard controller signal descriptionPIN ALE DBO DB7 GNDOn OFF Sub-CPU side ProcedureCRT inter face test Shared RAMAbnormal S C I I 00-FFReady O.H Abnormal test ending1 5 c * O DR O.7 ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart SEEK, Read Error Jump \ Boot Address SystemError Load Iocs SEEK& Read105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U URoB IwCAIO MZ-35OO Parts Guide LI S C R I P T I O N No Parts CodeLED PWB IE--or Ooss-zw Parts Code MZ-3500N T K QcnwS C R I P T I O N ConnectorNO. Parts Code MZ-3500Parts Code A a N a DNEW VH S N 7 4 0 6 NCoos Part S C R I P T I O NMark Rank M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitLSI RAM SOCLA a NO. Parts CodeD e Tin N a a Parts CodeMZ-3500 Sharp Corporation