Sharp MZ-3500 service manual MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit

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MZ3500

3-5. Memory (ROMIPL, RAMCOM, S-RAM) select circuit

To main CPU

1)ROM-IPL select by the main CPU

As ROM IPL turns to low level after power on address bus buffers (LS244, LS367) and data bus buffer (LS245) are enabled. S of the data selector 1C (LS157) is set to a low level to enable input 1A-4A. The 3Y and 2Y outputs of the LS157 then go low so that CE and OE of the ROM-IPL are from main CPU. The contents of the IPL-ROM are then read by the main CPU. Because the input pin (^16) of the address buffer (LS367) is connected to Vcc, IPL for the main CPU will be at address 1000 of the IPL-ROM. Switch SW2BA is the operation test dip switch which should be ON at all times.

2)RAM-COM select by the main CPU

When RAM COM is low, SRES high, and SACK low, the select input S of the selector 1C (LS157) is in low state so that input 1A-4A becomes effective. That is, the out- put 4Y is low and either 1Y (WE) or 2Y (OE) becomes low level, so asto enable to read or write RAM-COM.

3)ROM-IPL select by sub-CPU

Normally, the select signal S of the selector is pulled up to Vcc level that inputs 1B-4B are enabled by sub CPU. If A13 thru A15 were to be at low level, the output YO of the LS139 becomes low level so that the output 3Y of the LS147 or CE of the ROM-IPL should be at low level. Should SRD, SMRQ be at low lebel as well, the output 2Y of the LS157 or OE of the ROM-IPL turnde to low lebel to read the ROM-IPL. Though the sub-CPU can access an address range of 0000 to 1FFF theoretical- ly, it would be from 0000 to OFFF, actually.

4)RAM-COM select by sub-CPU

Y1 of the LS139 changes to low level when AS13 is high and AS14 and AS15 are low. In other words, the input 4B of the LS157 is at low level which brings the output Y4 to low level, so that CSof the RAM-COM chip select signal should become effective.

If SMRQ, SRD or SMRQ, SWR is in low level at this point, it enables read (OE) or write (WE). Address range, however, is 2000 to 3FFF

5)RAM (SA, SB, SC, SD) select by sub-CPU

SMRQ, SRD (Of) or SMRQ, SWR (WE) is at low level to select the sub-CPU dedicated RAM, SA-SD. Tne following chip select signal, then becomes valid under these conditions:

RAMSA .. ASVi, AS12, AS13, AS14, AST! (address 4000^17FF)

RAMSB .. AS11, AST2, AST3, AS14, AS15 (address 4800-4FFF)

RAMSC .. AS11, AS12, AS13, AS14, AS15 (address 5000-57FF)

RAMSD .. AS11, AS12, AS13, ASK, ASHi (address 5800-5FFF)

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Contents Personal Computer Model Z-350 BACKUP, INIT, COPY, DEBUG, Killall TimerMemory VideoSlot Slot2 Refer to the page TIN Circuit DiagramLSI, 1C Cmosic SFDI/FSymbol PresetSdisp Change DispBase Basic Area RAMSystem UserMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MBank Select FfffMAO Operational description SD3 RAM based BasicBank ROMMain Memory Mapper Block diagram Relation between MMR main memoryMain CPU and I/O port This paragraph discusses main CPU I/OTable below describes address map Main CPU \m 0001MZ3500 Sub CPU and I/O portTo Reset Memory mapper MMRSP6102R-001 Block diagramAddress BUS CoabMZ3500 Memory mapper MMR SP6102R-001 signal description RAS ROW Address Select Line Address Select SignalSrdy Pin No IN/OUT RO1BRO2B 1 1 1 1 0 KI1 Dl Do 17 D6 D5 A7 A6 A5A4A3A2AlAO H E X Uhus 1 OD2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationBlue Dot pitchDot color designated by Graphic dotCH AT KA7CH AI +,! AT A r + + G Ascii CG #1 FFFVideo RAM Structure of Vram Structure of character Vram When read/write from GDC #07FFA#0000 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KSetup of GCD master/slave 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzMaster/slave setup by combination O signal switchingGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description CSP-1 Block Diagram » CKCSH HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description3r00 CSP 2 Block DiagramDSP2 OUT CAS OUTGDC Graphic display controller UPD7220 signal description NK-CLC AD15ILC2AT~BTI CSR-1MAGEStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeCsrw C 49H -COMMAND Code Return when all parameters were sentWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty?Explanation 60HVECTE. Dot address is structured on the screen Following manner Dot display program example-1I T E C 23H P4 88H P5 HHKind of line solid line Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MZ350C Trigger motor on of the timer 555 Selects FDDPort used in the MFD interface is as follows MFM recording methodMedia detection Controls during read, write, seek, and re- calibrate3500 Precompensate Circuit Control during seek and recalibrationPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ Side = Aload3DSC \128 76 iy 7 EH 77 / FFHTrack 10 sector Indicates the byte position From the top of directoryB144 6145 B146 B147 39 B148 B149 B150 B151 Ii Patat39 B74 B75 1015Data transmission format General specificationMZS500 Example 7-bits, even parity, 1 stop bitAC controls StartOFF MZ3500 Data output control KTS8251 AC RXEN,UTR , T X E N 3SOO9 6.3 200256 128«--N Wl -»8253 OUT 8253AA3 Printer interfacing circuitDAT DS7General description of the parallel interface OutputData transfer timing I/O port map Read Hold Clock circuit SchematicWrite Hold SET DINLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilS I C 3500GP I/O SFD 1/FDipswa SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFSEC FD2\f Canbe in either state Block diagram FunctionsDescription of each block +5V Switching regulatorTiming chart Alarm generation circuitSpecification of keyboard control At rrnKey 2s 2s22 21 Key search timingKey Strobe132.5 22.5/-sProtocol Key to sub CPU Keyboard controller basic flow XTAL1 XTAL2 Reset INT Keyboard controller signal descriptionPIN ALE DBO DB7 GNDOn OFF Sub-CPU side ProcedureCRT inter face test Shared RAMAbnormal S C I I 00-FFAbnormal test ending 1 5 c * O DR O.7Ready O.H ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart SEEK, Read Error Jump \ Boot Address SystemError Load Iocs SEEK& Read105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U UIwC AIORoB MZ-35OO Parts Guide LI No Parts Code LED PWBS C R I P T I O N IE--or Ooss-zw Parts Code MZ-3500N T K QcnwS C R I P T I O N ConnectorNO. Parts Code MZ-3500Parts Code A a N a DNEW VH S N 7 4 0 6 NPart S C R I P T I O N Mark RankCoos M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitLSI RAM SOCLA a NO. Parts CodeD e Tin N a a Parts CodeMZ-3500 Sharp Corporation
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